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typical operating circuit 19-6534; rev 0; 12/12 ordering information appears at end of data sheet. general description the max8967 is an f pmic with two dc-to-dc step- down switching converters and six remote capaci - tor-capable ldos. the step-down converters deliv - er up to 2a of output current independently. two of the ldos deliver a load current up to 300ma, while the remaining four deliver up to 150ma. both step-down converters have remote sense, allowing loads to be placed away from the ic. the ic operates over a 2.6v to 5.5v input supply range. fixed-frequency 4.4mhz pwm operation and clocks that are 180 n out of phase permit the use of small external components. under light load conditions, the step-down converters automatically switch to skip mode operation. in skip mode operation, switching occurs only as need - ed, allowing efficient operation. placing either of the step- down converters into green mode reduces the quiescent current consumption of that converter to 5 f a (typ). the ic supports dynamic adjustment of the output voltage through its i 2 c interface. each step-down converter has two register settings for output voltage and a setting for ramp rate. also, each step-down converter has a dedicated enable pin and a dedicated v id pin to toggle between the two programmed output voltages. additionally, an interrupt output is provided, allowing the ic to signal its master. benefits and features s multi-output pmic in a compact package ? two 2a step-down converters with remote output voltage sensing ? two 300ma ldos ? four 150ma ldos ? < 1a shutdown current ? 2.32mm x 2.44mm package s versatile step-down converters ? programmable output voltage (0.6v to 3.3875v) through i 2 c bus ? programmable output voltage slew rate (12.5mv/s to 50mv/s) ? dynamic switching between two output voltages through v id_ pins s efficient step-down converters ? over 95% efficiency with internal synchronous rectifier ? automatic skip mode at light loads ? low 61a (typ) quiescent current ? 5a (typ) green mode per step-down converter s programmable ldos ? programmable output voltage (0.8v to 3.95v in 50mv steps) ? programmable soft-start slew rate (5mv/sC100mv/s) s reduces component size and board area solution ? 4.4mhz step-down switching allows for 1h inductors ? c out = 1f for all ldos ? reduced board space with remote capacitor ldos ? internal feedback for step-down converters and ldos applications cellular handsets and smartphones tablets portable devices note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maximintegrated.com/errata . v io in1 out1 lx1 pgnd1 inpu t 2.6v to 5.5v in2 av ina 1.7v to 5.5v 1.65v to 5.5v inb agnd i 2 c scl sda en1 en2 v id1 v id2 irqb 1h out2 lx2 pgnd2 ldo1 0.8v to 3.95v, 150ma ldo2 0.8v to 3.95v, 300ma ldo3 0.8v to 3.95v, 150ma ldo4 0.8v to 3.95v, 150ma ldo5 0.8v to 3.95v, 300ma ldo6 0.8v to 3.95v, 150ma 1h out1 0.6v to 3.3875v, 2a out2 0.6v to 3.3875v, 2a max8967 max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 2 in1, in2, ina, inb, av, out1, out2, ,scl, sda, snsp1, snsn1, snsp2, snsn2 to agnd .................... -0.3v to +6.0v en1, en2, v id_ , v io , irqb to agnd ...... -0.3v to (v av + 0.3v) ldo1, ldo2, ldo3 to agnd ................. -0.3v to (v ina + 0.3v) ldo4, ldo5, ldo6 to agnd ................. -0.3v to (v inb + 0.3v) pgnd1, pgnd2 to agnd ................................... -0.3v to +0.3v lx1, lx2 current .......................................................... 2.0a rms continuous power dissipation (t a = +70 n c) 30-bump, 2.32mm x 2.44mm wlp (derate 20.4mw/ n c above +70 n c) ............................ 1632mw operating temperature ...................................... -40 n c to +85 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c soldering temperature (reflow) ...................................... +260 n c wlp junction-to-ambient thermal resistance ( b ja ) .......... 49 n c/w junction-to-case thermal resistance ( b jc ) .................... 9 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) caution! esd sensitive device parameter symbol conditions min typ max units operating input voltage range v input v in1 = v in2 = v av 2.6 5.5 v overvoltage lockout ovp v av rising, 100mv hysteresis 5.70 5.85 6.00 v av undervoltage lockout (uvlo) uvlo v av rising, 55mv hysteresis 2.3 2.4 2.5 v v io operating range v io 1.65 5.5 v v io enable threshold high 1.4 v v io enable threshold low 0.4 v v io enable hysteresis 100 mv v a shutdown current v av > 2.6v, v io < 0.4v, en1 = en2 = 0 t a = +25 n c -5 +0.1 +0.5 f a t a = +85 n c 0.1 v a standby current v av > 2.6v, v io > 1.4v, en1 = en2 = 0 28 f a v io supply current all logic in high or low state 0.1 f a quiescent current (green mode) no switching, v out_ = 1.2v, step-down converter in green mode, all ldos off 5 f a quiescent current (step-down converters on) no switching, v out_ = 1.2v remote sense off 61 85 f a quiescent current (all on normal mode) no switching, v out_ = 1.2v, remote sense off, both step-down converters in normal mode, all ldos on 176 f a quiescent current (step-down converters on, normal mode remote sense on) no switching, v out_ = 1.2v, remote sense on, both step-down converters on 75 120 f a maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 3 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units quiescent current (all on green mode) no switching, v out_ = 1.2v, both step-down converters in green mode, all ldos on 40 f a fpwm current forced pwm, one step-down converter on only, i out = 0a, c out1 = c out2 = 22 f f, l1 = l2 = 1 f h, v out = 1.2v 9 ma thermal shutdown t a rising, 20 n c hysteresis +160 n c step-down converter 1 output current l = 1 f h 2 a adjustable output voltage range 12.5mv steps 0.6000 3.3875 v settling time fpwm, i out1 = 0.2a c out1 = 22 f f, l = 1 f h, measure from v out1 = 1v to v out1 = 1.2v 20 f s output voltage accuracy (fpwm) v out1 = 1.2v, fpwm, v out1 < 0.95 x v in , remote sense disabled (note 3) 1.176 1.20 1.224 v output voltage accuracy (green mode) green mode, i out1 p 5ma (note 3) 1.152 1.200 1.248 v line regulation v out1 = 1.2v, i out1 = 0.2a, c out1 = 22 f f, l = 1 f h 0.04 %/v load regulation v out1 = 1.2v, 0 p i out1 p 2a +0.125 %/a switching frequency 3.96 4.40 4.84 mhz peak current limit fpwm mode 2500 3000 3600 ma valley current limit fpwm mode 1800 ma negative current limit fpwm mode 1 a zero-crossing current threshold used in skip mode and green mode 20 ma pmos on-resistance v in_ = 3.6v, i out1 = 190ma 60 m i nmos on-resistance v in_ = 3.6v, i out1 = 190ma 50 m i lx leakage v lx1 = v in , 0v t a = +25 n c -1 0.1 +1 f a t a = +85 n c 1 output discharge resistor in shutdown feature must be active, see the register definitions section 100 i maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 4 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units output step ramp rate slew_ _[7:6] = 00, see table 15 12.5 mv/ f s slew_ _[7:6] = 01, see table 15 25 slew_ _[7:6] = 10, see table 15 50 load transient fpwm fpwm mode, v out1 = 1.2v, load steps between 0.2 to 1.2a in 30ns, c out1 = 22 f f, l = 1 f h 40 mv load transient (skip mode) skip mode, v out = 1.2v, load steps between 0.2 to 1.2a in 30ns, c out1 = 22 f f, l = 1 f h 40 mv line transient v out = 1.2v, i out1 = 1.2a, c out1 = 22 f f, l = 1 f h. 0.25 %/v overshoot transitions between output voltage states 1.0 and 1.4v, i out1 = 400ma, c out1 = 22 f f, l = 1 f h 40 mv chip enable time from chip standby state until first output voltage ramp starts 250 f s enable time from enabling until voltage ramp starts, the ic is in normal operating state with previous state shut down, i out1 p 100ma, l = 1 f h, c out1 = 22 f f 25 f s output pok threshold v out1 falling, 1.2v nominal setting 86 90 94 %v out1 output pok threshold hysteresis 3 % minimum output capacitance 12 f f minimum inductance 1 f h inductor with 30% duration 1 f h step-down converter 2 output current l = 1 f h 2 a adjustable output voltage range 12.5mv steps 0.6000 3.3875 v settling time fpwm, i out2 = 0.2a, c out2 = 22 f f, l = 1 f h, measure from v out2 = 1v to v out2 = 1.2v 20 f s output voltage accuracy (fpwm) v out2 = 1.2v, fpwm, v out2 < 0.95 x v in , remote sense disabled (note 3) 1.176 1.20 1.224 v output voltage accuracy (green mode) green mode, i out2 p 5ma (note 3) 1.152 1.200 1.248 v line regulation v out2 = 1.2v, i out2 = 0.2a, c out2 = 22 f f, l = 1 f h 0.04 %/v maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 5 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units load regulation v out2 = 1.2v, 0 p i out2 p 2a +0.125 %/a switching frequency 3.96 4.40 4.84 mhz peak current limit fpwm mode 2500 3000 3600 ma valley current limit fpwm mode 1800 ma negative current limit fpwm mode 1 a zero-crossing current threshold used in skip mode and green mode 20 ma pmos on-resistance v in_ = 3.6v, i out2 = 190ma 60 m i nmos on-resistance v in_ = 3.6v, i out2 = 190ma 50 m i lx leakage v lx2 = v in ,0v t a = +25 n c -1 0.1 +1 f a t a = +85 n c 1 output discharge resistor in shutdown feature must be active, see the register definitions section 100 i output step ramp rate slew_ _[7:6] = 00, see table 15 12.5 mv/ f s slew_ _[7:6] = 01, see table 15 25 slew_ _[7:6] = 10, see table 15 50 load transient fpwm fpwm mode, v out2 = 1.2v, load steps between 0.2 to 1.2a in 30ns, c out2 = 22 f f, l = 1 f h 40 mv load transient (skip mode) skip mode, v out2 = 1.2v, load steps between 0.2 to 1.2a in 30ns, c out2 = 22 f f, l = 1 f h 40 mv line transient v out2 = 1.2v, i out2 = 1.2a, c out2 = 22 f f, l = 1 f h 0.25 %/v overshoot transitions between output voltage states 1.0v and 1.4v, i out21 = 400ma, c out2 = 22 f f, l = 1 f h 40 mv chip enable time from chip standby state until first output voltage ramp starts 250 f s enable time from enabling until voltage ramp starts; the ic is in normal operating state with previous state shut down, i out2 p 100ma, l = 1 f h, c out2 = 22 f f 25 f s output pok threshold v out2 falling, 1.2v nominal setting 86 90 94 %v out2 output pok threshold hysteresis 3 % minimum output capacitance 12 f f minimum inductance 1 f h inductor with 30% duration 1 f h maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 6 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units ldo1 input voltage range v in,ldo1 1.7 5.5 v undervoltage lockout v uvlo,ldo1 v in,ldo1 rising, 100mv hysteresis 1.6 1.7 v output voltage range v out,ldo1 v inldo1 is the maximum of 3.7v or v out,ldo1 + 0.3v 0.8 3.95 v maximum output current i max,ldo1 normal mode 150 ma green mode 5 minimum output capacitance c out,ldo1 (note 4) normal mode 0.7 f f green mode 0.7 bias enable time t lbias1 time to enable ldo bias only, central bias is already enabled 90 f s bias enable currents i qbias1 ldo bias enabled, ldobiasen = 1 10 f a av supply current i av,ldo1 no load shutdown, t a = +25 n c (note 5) 0 f a normal regulation 3 6 green mode 0.5 3 ina input supply current i in,ldo1 no load shutdown, t a = +25 n c (note 6) 0 f a normal regulation 15 30 green mode 1 3 output voltage accuracy normal mode v in,ldo1 = v nom + 0.3v to 5.5v with 1.7v minimum, i out,ldo1 = 0.1ma to i max,ldo1 , v nom,ldo1 set to any voltage -3 +3 % green mode v in,ldo1 = v nom,ldo1 + 0.3v to 5.5v with 2.4v minimum, i out,ldo1 = 0.1ma to 5ma, v nom,ldo1 set to any voltage -5 +5 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 7 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units load regulation (note 7) normal mode i out,ldo1 = 0.1ma to i max,ldo1 , v in,ldo1 = v nom,ldo1 + 0.3v with 1.7v minimum, v nom,ldo1 set to any voltage 0.1 % green mode i out,ldo1 = 0.1ma to 5ma, v in,ldo1 = v nom,ldo1 + 0.3v with 2.4v minimum, v nom,ldo1 set to any voltage 0.2 line regulation (note 7) normal mode v in,ldo1 = v nom,ldo1 + 0.3v to 5.5v with 1.7v minimum, i out,ldo1 = 0.1ma, v nom,ldo1 set to any voltage 0.03 %/v green mode v in,ldo1 = v nom,ldo1 + 0.3v to 5.5v with 2.4v minimum, i out,ldo1 = 0.1ma, v nom,ldo1 set to any voltage 0.1 dropout voltage v do,ldo1 normal mode i out,ldo1 = i max,ldo1 v in,ldo1 = 3.7v 60 120 mv v in,ldo1 = 1.7v 150 300 green mode i out,ldo1 = 5ma, v in,ldo1 = 3.7v 50 100 output current limit i lim,ldo1 v out,ldo1 = 0v 150 225 375 ma output load transient (ldo1ovclmp_en = 1) (notes 4, 7 ) normal mode, v in,ldo1 = v nom,ldo1 + 0.3v to 5.5v with 1.7v absolute minimum, i out,ldo1 = 1% to 100% to 1% of i max,ldo1 , v nom,ldo1 set to any voltage, t r1 = t f1 = 1 f s, ldo1comp[5:4] = 01 66 mv green mode, v in,ldo1 = v nom,ldo1 + 0.3v to 5.5v with 2.4v absolute minimum, i out,ldo1 = 0.05ma to 5ma to 0.05ma, v nom,ldo1 set to any voltage, t r1 = t f1 = 1 f s 25 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 8 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units output line transient (notes 3, 6 ) normal mode, v in,ldo1 = v nom,ldo1 + 0.3v to v nom,ldo1 + 0.8v to v nom,ldo1 + 0.3v with 1.7v absolute minimum, t r1 = t f1 = 1 f s, i out,ldo1 = i max,ldo1 , v nom,ldo1 set to any voltage 5 mv green mode, v in,ldo1 = v nom,ldo1 + 0.3v to v nom,ldo1 + 0.8v to v nom,ldo1 + 0.3v with 2.4v absolute minimum, t r1 = t f1 = 1 f s, i out,ldo1 = 5ma, v nom,ldo1 set to any voltage 5 power-supply rejection psrr ldo1 rejection from v in,ldo1 to v out,ldo1 i out,ldo1 = 10% of i max,ldo1 v inldo1dc = v nom, ldo1 + 0.3v v inldo1ac = 50mv f = 1khz 63 db f = 10khz 51 f = 100khz 44 f = 1000khz 57 f = 4450khz 33 green mode, i out,ldo1 = 1ma, f = 1khz, rejection from v in,ldo1 to v out,ldo1 50 output noise f = 10hz to 100khz, i out,ldo1 = 10% of i max,ldo1 v out,ldo1 = 0.8v 45 f v rms v out,ldo1 = 1.8v 45 v out,ldo1 = 3.7v 60 startup ramp rate t ss,ldo1 after enabling ldo1ss = 0 100 mv/ f s ld01ss = 1 5 active-discharge resistance v out,ldo1 = 1v, output disabled active discharge enabled, ldo1ade = 1 0.16 0.3 k i active discharge disabled, ldo1ade = 0 1000 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 9 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units clamp active regulation voltage clamp active (ldo1ovclmp_en = 1), ldo output sinking 0.1ma v nom, ldo1 v clamp disabled overvoltage sink current v out,ldo1 = v nom,ldo1 x 110% 2.2 f a enable delay (note 4) t lon,ldo1 time from ldo enable command received to the output starting to slew ramp rate = 100mv/ f s 10 f s ramp rate = 5mv/ f s 60 disable delay (note 4) after ldo is disabled; the ldo output voltage discharges based on load and c out ; to ensure fast discharge times, enable the active discharge resistor 0.1 f s transition time from green mode to normal mode 10 f s thermal shutdown output disabled or enabled t j rising 165 n c t j falling 150 power-ok threshold v pokthl1 v out,ldo1 when v pok switches v out,ldo1 rising 92 95 % v out,ldo1 falling 84 87 power-ok noise pulse immunity v poknf1 v out,ldo1 pulsed from 100% to 80% of regulation 25 f s ldo2 input voltage range v in,ldo2 1.7 5.5 v undervoltage lockout v uvlo, ldo2 v in,ldo2 rising, 100mv hysteresis 1.6 1.7 v output voltage range v out, ldo2 v in,ldo2 is the maximum of 3.7v or v out,ldo2 + 0.3v 0.8 3.95 v maximum output current i max,ldo2 normal mode 300 ma green mode 5 minimum output capacitance c out, ldo2 (note 3) normal mode 0.7 f f green mode 0.7 bias enable time t lbias2 time to enable ldo bias only, central bias is already enabled 90 f s bias enable current i lbias2 ldo bias enabled 10 f a maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 10 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units av supply current i av,ldo2 no load shutdown, t a = +25 n c (note 5) 0 f a normal regulation 3 6 green mode 0.5 3 ina supply current i in,ldo2 no load shutdown, t a = +25 n c (note 5) 0 f a normal regulation 17 30 green mode 1 3 output voltage accuracy normal mode v in,ldo2 = v nom,ldo2 + 0.3v to 5.5v with 1.7v minimum, i out,ldo2 = 0.1ma to i max,ldo2 , v nom,ldo2 set to any voltage -3 +3 % green mode v in,ldo2 = v nom,ldo2 + 0.3v to 5.5v with 2.4v minimum, i out,ldo2 = 0.1ma to 5ma, v nom,ldo2 set to any voltage -5 +5 load regulation (note 6) normal mode i out,ldo2 = 0.1ma to i max,ldo2 , v in,ldo2 = v nom,ldo2 + 0.3v with 1.7v minimum, v nom,ldo2 set to any voltage 0.1 % green mode i out,ldo2 = 0.1ma to 5ma, v in,ldo2 = v nom,ldo2 + 0.3v with 2.4v minimum, v nom,ldo2 set to any voltage 0.2 line regulation (note 6) normal mode v in,ldo2 = v nom,ldo2 + 0.3v to 5.5v with 1.7v minimum; i out,ldo2 = 0.1ma, v nom,ldo2 set to any voltage 0.03 %/v green mode v in,ldo2 = v nom,ldo2 + 0.3v to 5.5v with 2.4v minimum; i out,ldo2 = 0.1ma, v nom,ldo2 set to any voltage 0.1 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 11 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units dropout voltage v do,ldo2 normal mode i out,ldo2 = i max,ldo2 v in,ldo2 = 3.7v 50 100 mv v in,ldo2 = 1.7v 150 450 green mode i out,ldo2 = 5ma, v in,ldo2 = 3.7v 150 300 output current limit i lim,ldo2 v out,ldo2 = 0v 300 450 750 ma output load transient (ldo2ovclmp_en = 1) (notes 3, 6 ) normal mode, v in,ldo2 = v nom,ldo2 + 0.3v to 5.5v with 1.7v absolute minimum; i out,ldo2 = 1% to 100% to 1% of i max,ldo2 , v nom,ldo2 set to any voltage, t r2 = t f2 = 1 f s, ldo2comp[5:4] = 01 66 mv green mode, v in , ldo2 = v nom,ldo2 + 0.3v to 5.5v with 2.4v absolute minimum; i out,ldo2 = 0.05ma to 5ma to 0.05ma, v nom,ldo2 set to any voltage, t r2 = t f2 = 1 f s 25 output line transient (notes 3, 6 ) normal mode, v in,ldo2 = v nom,ldo2 + 0.3v to v nom,ldo2 + 0.8v to v nom,ldo2 + 0.3v with 1.7v absolute minimum; t r2 = t f2 = 1 f s, i out,ldo2 = i max,ldo2 , v nom,ldo2 set to any voltage 5 mv green mode, v in,ldo2 = v nom,ldo2 + 0.3v to v nom,ldo2 + 0.8v to v nom,ldo2 + 0.3v with 2.4v absolute minimum; t r2 = t f2 = 1 f s, i out,ldo2 = 5ma, v nom,ldo2 set to any voltage 5 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 12 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units power-supply rejection psrr ldo2 rejection from v in,ldo2 to v out,ldo2 i out,ldo2 = 10% of i max,ldo2 v inldo2dc = v nom,ldo2 +0.3v v inldo2ac = 50mv f = 1khz 63 db f = 10khz 51 f = 100khz 44 f = 1000khz 57 f = 4450khz 33 green mode, i out,ldo2 = 1ma, f = 1khz, rejection from v in,ldo2 to v out,ldo2 50 output noise f = 10hz to 100khz, i out,ldo2 = 10% of i max,ldo2 v out,ldo2 = 0.8v 45 f v rms v out,ldo2 = 1.8v 45 v out,ldo2 = 3.7v 60 startup ramp rate t ss22 after enabling ldo2ss = 0 100 mv/ f s ldo2ss = 1 5 active-discharge resistance v out,ldo2 = 1v, output disabled active discharge enabled, ldo2ade = 1 0.16 0.3 k i active discharge disabled, ldo2ade = 0 1000 clamp active regulation voltage clamp active (ldo2ovclmp_en = 1), ldo output sinking 0.1ma v nom, ldo2 v clamp disabled overvoltage sink current v out,ldo2 = v nom,ldo2 x 110% 2.2 f a enable delay (note 3) t lon2 time from ldo enable command received to the output starting to slew ramp rate = 100mv/ f s 10 f s ramp rate = 5mv/ f s 60 disable delay (note 3) after ldo is disabled; the ldo output voltage discharges based on load and c out ; to ensure fast discharge times, enable the active discharge resistor 0.1 f s maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 13 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units transition time from green mode to normal mode 10 f s thermal shutdown output disabled or enabled t j rising 165 n c t j falling 150 power-ok threshold v pokthl2 v out,ldo2 when v pok switches v out,ldo2 rising 92 95 % v out,ldo2 falling 84 87 power-ok noise pulse immunity v poknf2 v out,ldo2 pulsed from 100% to 80% of regulation 25 f s ldo3 input voltage range v in,ldo3 1.7 5.5 v undervoltage lockout v uvlo, ldo3 v in,ldo3 rising, 100mv hysteresis 1.6 1.7 v output voltage range v out, ldo3 v in,ldo3 is the maximum of 3.7v or v out,ldo3 + 0.3v 0.8 3.95 v maximum output current i max,ldo3 normal mode 150 ma green mode 5 minimum output capacitance c out, ldo3 (note 3) normal mode 0.7 f f green mode 0.7 bias enable time t lbias3 time to enable ldo bias only, central bias is already enabled 90 f s bias enable currents i qbias3 ldo bias enabled 10 f a av supply current i av,ldo3 no load shutdown, t a = +25 n c (note 4) 0 f a normal regulation 3 6 green mode 0.5 3 ina supply current i in,ldo3 no load shutdown, t a = +25 n c (note 5) 0 f a normal regulation 15 30 green mode 1 3 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 14 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units output voltage accuracy normal mode v in,ldo3 = v nom,ldo3 + 0.3v to 5.5v with 1.7v minimum, i out,ldo3 = 0.1ma to i max,ldo3 , v nom,ldo3 set to any voltage -3 +3 % green mode v in,ldo3 = v nom,ldo3 + 0.3v to 5.5v with 2.4v minimum, i out,ldo3 = 0.1ma to 5ma, v nom,ldo3 set to any voltage -5 +5 load regulation (note 6) normal mode i out,ldo3 = 0.1ma to i max,ldo3 , v in,ldo3 = v nom,ldo3 + 0.3v with 1.7v minimum, v nom,ldo3 set to any voltage 0.1 % green mode i out,ldo3 = 0.1ma to 5ma, v in,ldo3 = v nom,ldo3 + 0.3v with 2.4v minimum, v nom,ldo3 set to any voltage 0.2 line regulation (note 6) normal mode v in,ldo3 = v nom,ldo3 + 0.3v to 5.5v with 1.7v minimum, i out,ldo3 = 0.1ma, v nom,ldo3 set to any voltage 0.03 %/v green mode v in,ldo3 = v nom,ldo3 + 0.3v to 5.5v with 2.4v minimum, i out,ldo3 = 0.1ma, v nom,ldo3 set to any voltage 0.1 dropout voltage v do,ldo3 normal mode i out,ldo3 = i max,ldo3 v in,ldo3 = 3.7v 60 120 mv v in,ldo3 = 1.7v 150 300 green mode i out,ldo3 = 5ma, v in,ldo3 = 3.7v 50 100 output current limit i lim,ldo3 v out = 0v 150 225 375 ma maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 15 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units output load transient (ldo3ovclmp_en = 1) (notes 3, 6 ) normal mode, v in,ldo3 = v nom,ldo3 + 0.3v to 5.5v with 1.7v absolute minimum, i out,ldo3 = 1% to 100% to 1% of i max,ldo3 , v nom,ldo3 set to any voltage, t r3 = t f3 = 1 f s, ldo3comp[5:4] = 01 66 mv green mode, v in,ldo3 = v nom,ldo3 + 0.3v to 5.5v with 2.4v absolute minimum, i out,ldo3 = 0.05ma to 5ma to 0.05ma, v nom,ldo3 set to any voltage, t r3 = t f3 = 1 f s 25 output line transient (notes 3, 6 ) normal mode, v in,ldo3 = v nom,lod3 + 0.3v to v nom,ldo3 + 0.8v to v nom,ldo3 + 0.3v with 1.7v absolute minimum, t r3 = t f3 = 1 f s, i out,lod3 = i max,ldo3 , v nom,lod3 set to any voltage 5 mv green mode, v in,ldo3 = v nom,lod3 + 0.3v to v nom,ldo3 + 0.8v to v nom,ldo3 + 0.3v with 2.4v absolute minimum, t r3 = t f3 =1 f s, i out,lod3 = 5ma, v nom,lod3 set to any voltage 5 power-supply rejection psrr ldo3 rejection from v in,ldo3 to v out,ldo3 i out,ldo3 = 10% of i max,ldo3 v inldo3dc = v nom,ldo3 + 0.3v v inldo3ac = 50mv f = 1khz 63 db f = 10khz 51 f = 100khz 44 f = 1000khz 57 f = 4450khz 33 green mode, i out,ldo3 = 1ma, f = 1khz, rejection from v in,ldo3 to v out,ldo3 50 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 16 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units output noise f = 10hz to 100khz, i out = 10% of i max,ldo3 v out,ldo3 = 0.8v 45 f v rms v out,ldo3 = 1.8v 45 v out,ldo3 = 3.7v 60 startup ramp rate t ss3 after enabling ldo3ss = 0 100 mv/ f s ldo3ss = 1 5 active-discharge resistance v out,ldo3 = 1v, output disabled active discharge enabled, ldo3ade = 1 0.16 0.3 k i active discharge disabled, ldo3ade = 0 1000 clamp active regulation voltage clamp active (ldo3ovclmp_en = 1), ldo output sinking 0.1ma v nom, ldo3 v clamp disabled overvoltage sink current v out,ldo3 = v nom,ldo3 x110% 2.2 f a enable delay (note 3) t lon3 time from ldo enable command received to the output starting to slew ramp rate = 100mv/ f s 10 f s ramp rate = 5mv/ f s 60 disable delay (note 3) after ldo is disabled; the ldo output voltage discharges based on load and c out,ldo3 ; to ensure fast discharge times enable the active discharge resistor 0.1 f s transition time from green mode to normal mode 10 f s thermal shutdown output disabled or enabled t j rising 165 n c t j falling 150 power-ok threshold v pokthl3 v out,ldo3 when v pok switches v out,ldo3 rising 92 95 % v out,ldo3 falling 84 87 power-ok noise pulse immunity v poknf3 v out,ldo3 pulsed from 100% to 80% of regulation 25 f s ldo4 input voltage range v in,ldo4 1.7 5.5 v undervoltage lockout v uvlo, ldo4 v in,ldo4 rising, 100mv hysteresis 1.6 1.7 v output voltage range v out, ldo4 v in,ldo4 is the maximum of 3.7v or v out,ldo4 + 0.3v 0.8 3.95 v maximum output current i max,ldo4 normal mode 150 ma green mode 5 minimum output capacitance c out, ldo4 (note 3) normal mode 0.7 f f green mode 0.7 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 17 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units bias enable time t lbias4 time to enable ldo bias only, central bias is already enabled 90 f s bias enable currents i qbias4 ldo bias enabled 10 f a av supply current i av,ldo4 no load shutdown, t a = +25 n c (note 4) 0 f a normal regulation 3 6 green mode 0.5 3 inb supply current i in,ldo4 no load shutdown, t a = +25 n c (note 5) 0 f a normal regulation 15 30 green mode 1 3 output voltage accuracy normal mode v in,ldo4 = v nom,ldo4 + 0.3v to 5.5v with 1.7v minimum, i out,ldo4 = 0.1ma to i max,ld04 , v nom,ldo4 set to any voltage -3 +3 % green mode v in,ldo4 = v nom,ldo4 + 0.3v to 5.5v with 2.4v minimum, i out,ldo4 = 0.1ma to 5ma, v nom,ldo4 set to any voltage -5 +5 load regulation (note 6) normal mode i out,ldo4 = 0.1ma to i max,ld04 , v in = v nom,ldo4 + 0.3v with 1.7v minimum, v nom,ldo4 set to any voltage 0.1 % green mode i out,ldo4 = 0.1ma to 5ma, v in = v nom,ldo4 + 0.3v with 2.4v minimum, v nom,ldo4 set to any voltage 0.2 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 18 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units line regulation (note 6) normal mode v in,ldo4 = v nom,ldo4 + 0.3v to 5.5v with 1.7v minimum, i out,ldo4 = 0.1ma, v nom,ldo4 set to any voltage 0.03 %/v green mode v in,ldo4 = v nom,ldo4 + 0.3v to 5.5v with 2.4v minimum, i out,ldo4 = 0.1ma, v nom,ldo4 set to any voltage 0.1 dropout voltage v do,ldo4 normal mode i out,ldo4 = i max,ld04 v in,ldo4 = 3.7v 60 120 mv v in,ldo4 = 1.7v 150 300 green mode i out,ldo4 = 5ma, v in,ldo4 = 3.7v 50 100 output current limit i lim,ldo4 v out,ldo4 = 0v 150 225 375 ma output load transient (ldo4ovclmp_en = 1) (notes 3, 6 ) normal mode, v in,ldo4 = v nom,ldo4 + 0.3v to 5.5v with 1.7v absolute minimum. i out,ldo4 = 1% to 100% to 1% of i max,ldo4 , v nom,ld04 set to any voltage, t r4 = t f4 = 1 f s, ldo4comp[5:4] = 01 66 mv green mode, v in,ldo4 = v nom,ldo4 + 0.3v to 5.5v with 2.4v absolute minimum, i out,ldo4 = 0.05ma to 5ma to 0.05ma, v nom,ldo4 set to any voltage, t r4 = t f4 = 1 f s 25 output line transient (notes 3, 6 ) normal mode, v in,ldo4 = v nom,ldo4 + 0.3v to v nom,ldo4 + 0.8v to v nom,ldo4 + 0.3v with 1.7v absolute minimum, t r4 = t f4 = 1 f s, i out,ldo4 = i max,ldo4 , v nom,ldo4 set to any voltage 5 mv green mode, v in,ldo4 = v nom,ldo4 + 0.3v to v nom,ldo4 + 0.8v to v nom,ldo4 + 0.3v with 2.4v absolute minimum, t r4 = t f4 = 1 f s, i out,ldo4 = 5ma, v nom,ldo4 set to any voltage 5 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 19 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units power-supply rejection psrr ldo4 rejection from v in,ldo4 to v out,ldo4 i out,ldo4 = 10% of i max,ldo4 v inldo4dc = v nom,ldo4 + 0.3v, v inldo4ac = 50mv f = 1khz 63 db f = 10khz 51 f = 100khz 44 f = 1000khz 57 f = 4450khz 33 green mode, i out,ldo4 = 1ma, f = 1khz, rejection from v in,ldo4 to v out,ldo4 50 output noise f = 10hz to 100khz, i out = 10% of i max v out = 0.8v 45 f v rms v out = 1.8v 45 v out = 3.7v 60 startup ramp rate t ss4 after enabling ldo4ss = 0 100 mv/ f s ldo4ss = 1 5 active-discharge resistance v out,ldo4 = 1v, output disabled active discharge enabled, ldo4ade = 1 0.16 0.3 k i active discharge disabled, ldo4ade = 0 1000 clamp active regulation voltage clamp active (ldo4ovclmp_en = 1), ldo output sinking 0.1ma v nom, ldo4 v clamp disabled overvoltage sink current v out,ldo4 = v nom,ldo4 x 110% 2.2 f a enable delay (note 3) t lon4 time from ldo enable command received to the output starting to slew ramp rate = 100mv/ f s 10 f s ramp rate = 5mv/ f s 60 disable delay (note 3) after ldo is disabled; the ldo output voltage discharges based on load and c out,ldo4 ; to ensure fast discharge times enable the active discharge resistor 0.1 f s transition time from green mode to normal mode 10 f s thermal shutdown output disabled or enabled t j rising 165 n c t j falling 150 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 20 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units power-ok threshold v pokthl4 v out,ldo4 when v pok switches v out,ldo4 rising 92 95 % v out,ldo4 falling 84 87 power-ok noise pulse immunity v poknf4 v out,ldo4 pulsed from 100% to 80% of regulation 25 f s ldo5 input voltage range v in,ldo5 1.7 5.5 v undervoltage lockout v uvlo, ldo5 v in,ldo5 rising, 100mv hysteresis 1.6 1.7 v output voltage range v out, ldo5 v in,ldo5 is the maximum of 3.7v or v out,ldo5 + 0.3v 0.8 3.95 v maximum output current i max,ldo5 normal mode 300 ma green mode 5 minimum output capacitance c out,ldo5 (note 3) normal mode 0.7 f f green mode 0.7 bias enable time t lbias5 time to enable ldo bias only, central bias is already enabled 90 f s bias enable currents i qbias5 ldo bias enabled 10 f a av supply current i av,ldo5 no load shutdown, t a = +25 n c (note 4) 0 f a normal regulation 3 6 green mode 0.5 3 inb supply current i in,ldo5 no load shutdown, t a = +25 n c (note 5) 0 f a normal regulation 17 30 green mode 1 3 output voltage accuracy normal mode v in,ldo5 = v nom,ldo5 + 0.3v to 5.5v with 1.7v minimum, i out,ldo5 = 0.1ma to i max,ldo5 , v nom,ldo5 set to any voltage -3 +3 % green mode v in,ldo5 = v nom,ldo5 + 0.3v to 5.5v with 2.4v minimum, i out,ldo5 = 0.1ma to 5ma, v nom,ldo5 set to any voltage -5 +5 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 21 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units load regulation (note 6) normal mode i out,ldo5 = 0.1ma to i max,ldo5 , v in,ldo5 = v nom,ldo5 + 0.3v with 1.7v minimum, v nom,ldo5 set to any voltage 0.1 % green mode i out,ldo5 = 0.1ma to 5ma, v in,ldo5 = v nom,ldo5 + 0.3v with 2.4v minimum, v nom,ldo5 set to any voltage 0.2 line regulation (note 6) normal mode v in,ldo5 = v nom,ldo5 + 0.3v to 5.5v with 1.7v minimum. i out,ldo5 = 0.1ma, v nom,ldo5 set to any voltage 0.03 %/v green mode v in,ldo5 = v nom,ldo5 + 0.3v to 5.5v with 2.4v minimum. i out,ldo5 = 0.1ma, v nom,ldo5 set to any voltage 0.1 dropout voltage v do,ldo5 normal mode i out,ldo5 = i max,ldo5 v in,ldo5 = 3.7v 50 100 mv v in,ldo5 = 1.7v 150 450 green mode i out,ldo5 = 5ma, v in,ldo5 = 3.7v 150 300 output current limit i lim,ldo5 v out,ldo5 = 0v 300 450 750 ma output load transient (ldo5ovclmp_en = 1) (notes 3, 6 ) normal mode, v in,ldo5 = v nom,ldo5 + 0.3v to 5.5v with 1.7v absolute minimum, i out,ldo5 = 1% to 100% to 1% of i max,ldo5 , v nom,ldo5 set to any voltage, t r5 = t f5 = 1 f s, ldo5comp[5:4] = 01 66 mv green mode, v in,ldo5 = v nom,ldo5 + 0.3v to 5.5v with 2.4v absolute minimum, i out,ldo5 = 0.05ma to 5ma to 0.05ma, v nom,ldo5 set to any voltage, t r5 = t f5 = 1 f s 25 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 22 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units output line transient (notes 3, 6 ) normal mode, v in,lod5 = v nom,ldo5 + 0.3v to v nom,ldo5 + 0.8v to v nom,ldo5 + 0.3v with 1.7v absolute minimum, t r5 = t f5 = 1 f s, i out,ldo5 = i max,ldo5 , v nom,ldo5 set to any voltage 5 mv green mode, v in,ldo5 = v nom,ldo5 + 0.3v to v nom,ldo5 + 0.8v to v nom,ldo5 + 0.3v with 2.4v absolute minimum, t r5 = t f5 = 1 f s, i out,ldo5 = 5ma, v nom,ldo5 set to any voltage 5 power-supply rejection psrr ldo5 rejection from v in,ldo5 to v out,ldo5 i out,ldo5 = 10% of i max,ldo5 v inldo5dc = v nom,ldo5 + 0.3v v inldo5ac = 50mv f = 1khz 63 db f = 10khz 51 f = 100khz 44 f = 1000khz 57 f = 4450khz 33 green mode, i out = 1ma, f = 1khz, rejection from v in,ldo5 to v out,ldo5 50 output noise f = 10hz to 100khz, i out = 10% of i max,ldo5 v out,ldo5 = 0.8v 45 f v rms v out,ldo5 = 1.8v 45 v out,ldo5 = 3.7v 60 startup ramp rate t ss5 after enabling ldo5ss = 0 100 mv/ f s ldo5ss = 1 5 active-discharge resistance v out,ldo5 = 1v, output disabled active discharge enabled, ldo5ade = 1 0.16 0.3 k i active discharge disabled, ldo5ade = 0 1000 clamp active regulation voltage clamp active (ldo5ovclmp_en = 1), ldo output sinking 0.1ma v nom, ld05 v maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 23 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units clamp disabled overvoltage sink current v out,ldo5 = v nom,ldo5 x 110% 2.2 f a enable delay (note 3) t lon5 time from ldo enable command received to the output starting to slew ramp rate =100mv/ f s 10 f s ramp rate = 5mv/ f s 60 disable delay (note 3) after ldo is disabled; the ldo output voltage discharges based on load and c out ; to ensure fast discharge times, enable the active discharge resistor 0.1 f s transition time from green mode to normal mode 10 f s thermal shutdown output disabled or enabled t j rising 165 n c t j falling 150 power-ok threshold v pokthl v out,ldo5 when v pok switches v out,ldo5 rising 92 95 % v out,ldo5 falling 84 87 power-ok noise pulse immunity v poknf v out,ldo5 pulsed from 100% to 80% of regulation 25 f s ldo6 input voltage range v in,ldo6 1.7 5.5 v undervoltage lockout v uvlo,ldo6 rising, 100mv hysteresis 1.6 1.7 v output voltage range v out,ldo6 v in,ldo6 is the maximum of 3.7v or v out,ldo6 + 0.3v 0.8 3.95 v maximum output current i max,ldo6 normal mode 150 ma green mode 5 minimum output capacitance c out,ldo6 (note 3) normal mode 0.7 f f green mode 0.7 bias enable time t lbias6 time to enable ldo bias only, central bias is already enabled 90 f s bias enable currents i qbias6 ldo bias enabled 10 f a av supply current i av,ldo6 no load shutdown, t a = +25 n c (note 4) 0 f a normal regulation 3 6 green mode 0.5 3 inb supply current i in,ldo6 no load shutdown, t a = +25 n c (note 5) 0 f a normal regulation 15 30 green mode 1 3 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 24 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units output voltage accuracy normal mode v in,ldo6 = v nom,ldo6 + 0.3v to 5.5v with 1.7v minimum, i out,ldo6 = 0.1ma to i max,ldo6 , v nom,ldo6 set to any voltage -3 +3 % green mode v in,ldo6 = v nom,ldo6 + 0.3v to 5.5v with 2.4v minimum, i out,ldo6 = 0.1ma to 5ma, v nom,ldo6 set to any voltage -5 +5 load regulation (note 6) normal mode i out,ldo6 = 0.1ma to i max,ldo6 , v in,ldo6 = v nom,ldo6 + 0.3v with 1.7v minimum, v nom,ldo6 set to any voltage 0.1 % green mode i out,ldo6 = 0.1ma to 5ma, v in,ldo6 = v nom,ldo6 + 0.3v with 2.4v minimum, v nom,ldo6 set to any voltage 0.2 line regulation (note 6) normal mode v in,ldo6 = v nom,ldo6 + 0.3v to 5.5v with 1.7v minimum, i out,ldo6 = 0.1ma, v nom,ldo6 set to any voltage 0.03 %/v green mode v in,ldo6 = v nom,ldo6 + 0.3v to 5.5v with 2.4v minimum, i out,ldo6 = 0.1ma, v nom,ldo6 set to any voltage 0.1 dropout voltage v do,ldo6 normal mode i out,ldo6 = i max,ldo6 v in,ldo6 = 3.7v 60 120 mv v in,ldo6 = 1.7v 150 300 green mode i out,ldo6 = 5ma, v in,ldo6 = 3.7v 50 100 output current limit i lim,ldo6 v out,ldo6 = 0v 150 225 375 ma maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 25 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units output load transient (ldo6ovclmp_en = 1) (notes 3, 6 ) normal mode, v in,ldo6 = v nom,ldo6 + 0.3v to 5.5v with 1.7v absolute minimum, i out,ldo6 = 1% to 100% to 1% of i max,ldo6 , v nom,ldo6 set to any voltage, t r6 = t f6 = 1 f s, ldo6comp[5:4] = 01 66 mv green mode, v in,ldo6 = v nom,ldo6 +0.3v to 5.5v with 2.4v absolute minimum, i out,ldo6 = 0.05ma to 5ma to 0.05ma, v nom,ldo6 set to any voltage, t r6 = t f6 = 1 f s 25 output line transient (notes 3, 6 ) normal mode, v in,ldo6 = v nom,ldo6 + 0.3v to v nom,dlo6 + 0.8v to v nom,ldo6 + 0.3v with 1.7v absolute minimum, t r6 = t f6 = 1 f s, i out,ldo6 = i max,ldo6 , v nom,ldo6 set to any voltage 5 mv normal mode, v in,ldo6 = v nom,ldo6 + 0.3v to v nom,dlo6 + 0.8v to v nom,ldo6 + 0.3v with 2.4v absolute minimum, t r6 = t f6 = 1 f s, i out,ldo6 = 5ma, v nom,ldo6 set to any voltage 5 power-supply rejection psrr ldo6 rejection from v in,ldo6 to v out,ldo06 i out,ldo6 = 10% of i max,ldo6 v inlod6dc = v nom,ldo6 + 0.3v, v inldo6ac = 50mv f = 1khz 63 db f = 10khz 51 f = 100khz 44 f = 1000khz 57 f = 4450khz 33 green mode, i out,ldo6 = 1ma, f = 1khz, rejection from v in,ldo6 to v out,ldo6 50 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 26 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) parameter symbol conditions min typ max units output noise f = 10hz to 100khz, i out,ldo6 = 10% of i max,ldo6 v out,ldo06 = 0.8v 45 f v rms v out,ldo06 = 1.8v 45 v out,ldo06 = 3.7v 60 startup ramp rate t ss,ldo6 after enabling ldo6ss = 0 100 mv/ f s ldo6ss = 1 5 active-discharge resistance v out,ldo6 = 1v, output disabled active discharge enabled, ldo6ade = 1 0.16 0.3 k i active discharge disabled, ldo6ade = 0 1000 clamp active regulation voltage clamp active (ldo6ovclmp_en = 1), ldo output sinking 0.1ma v nom, ldo6 v clamp disabled overvoltage sink current v out,ldo6 = v nom,ldo6 x 110% 2.2 f a enable delay (note 3) t lon6 time from ldo enable command received to the output starting to slew ramp rate = 100mv/ f s 10 f s ramp rate = 5mv/ f s 60 disable delay (note 3) after ldo is disabled, the ldo output voltage discharges based on load and c out,ldo6 ; to ensure fast discharge times, enable the active discharge resistor 0.1 f s transition time from green mode to normal mode 10 f s thermal shutdown output disabled or enabled t j rising 165 n c t j falling 150 power-ok threshold v pokthl6 v out,ldo6 when v pok switches v out, ldo6 rising 92 95 % v out,ldo6 falling 84 87 power-ok noise pulse immunity v poknf6 v out,ldo6 pulsed from 100% to 80% of regulation 25 f s digital i/o logic input high voltage threshold v ih v id_ , en_, sda, scl, v in1 = v in2 = v av = 2.6v to 5.5v v io = 1.65v to 3.6v 1.4 v logic input low voltage threshold v il v id_ , en_, sda, scl, v in1 = v in2 = v av = 2.6v to 5.5v v io = 1.65v to 3.6v 0.4 v maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 27 electrical characteristics (continued) (v in _ = v av = 3.6v, v io = 1.8v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are t a = +25 n c.) (note 2) note 2: specifications are 100% production tested at t a = +25 n c. limits over the operating temperature range are guaranteed by design and characterization. ldo_comp = 01 (default). note 3: v out is limited to approximately: v in - (inductor dcr + output trace resistance + 100m i ) x i out . note 4: values are based on simulations and bench testing; they are not production tested. note 5: system shutdown current is guaranteed by testing the combined current part in shutdown in the main bias section. note 6: in shutdown current is guaranteed by testing the combined current of all in_ and ldo_ pins in shutdown to a 5 f a (max). note 7: does not include esr of the capacitance or trace resistance of the module/pcb. parameter symbol conditions min typ max units logic input current (sda, scl) v il = 0v or v ih = 3.6v, en_ = agnd t a = +25 n c -1 +1 f a t a = +85 n c 0.1 logic input current (v id_ , en_) v il = 0v, en_ = agnd t a = +25 n c -1 +1 f a t a = +85 n c 0.1 v id_ , en_ logic input pulldown resistor 400 k i i 2 c interface sda output low voltage i sda = 3ma 0.1 v i 2 c clock frequency 400 khz bus-free time between start and stop t buf see figure 7 in the digital i/o section 1.3 f s hold time repeated start condition t hd_sta see figure 7 in the digital i/o section 0.6 0.1 f s scl low period t low see figure 7 in the digital i/o section 1.3 0.2 f s scl high period t high see figure 7 in the digital i/o section 0.6 0.1 f s setup time repeated start condition t su_sta see figure 7 in the digital i/o section 0.6 0.1 f s sda hold time t hd_dat see figure 7 in the digital i/o section 0 -0.01 f s sda setup time t su_dat see figure 7 in the digital i/o section 0.1 0.05 f s glitch filter maximum pulse width of spikes that must be suppressed by the input filter of both the data and clk pins 50 ns setup time for stop condition t su_sto see figure 7 in the digital i/o section 0.6 0.1 f s maxim integrated
28 typical operating characteristics (v in_ = v av = 3.6v, v io = 1.8v, typical application circuit , t a = +25 n c, unless otherwise noted.) input supply current vs. input voltage max8967 toc01 input voltage (v) input current (ua) 4.5 3.5 5 10 15 20 25 30 35 40 45 50 55 60 0 2.5 5.5 step-down 1 in green mode, pfm ldos disabled input supply current vs. input voltage max8967 toc02 input voltage (v) input current (ua) 4.5 3.5 5 10 15 20 25 30 35 40 45 50 55 60 0 2.5 5.5 step-down 1 with remote sense off, pfm ldos disabled input supply current vs. input voltage max8967 toc03 input voltage (v) input current (ua) 4.5 3.5 5 10 15 20 25 30 35 40 45 50 55 60 0 2.5 5.5 step-down 1 with remote sense on, pfm ldos disabled input supply current vs. input voltage max8967 toc04 input voltage (v) input current (ua) 4.5 3.5 5 10 15 20 25 30 35 40 45 50 55 60 0 2.5 5.5 step-downs disabled v out , ldo1 = 1v in green mode input supply current vs. input voltage max8967 toc05 input voltage (v) input current (ua) 4.5 3.5 5 10 15 20 25 30 35 40 45 50 55 60 0 2.5 5.5 step-downs disabled v out , ldo1 = 1v in normal mode input supply current vs. input voltage max8967 toc06 input voltage (v) input current (ua) 4.5 3.5 5 10 15 20 25 30 35 40 45 50 55 60 0 2.5 5.5 step-downs in green mode ldos1 = 1v in green mode standby current vs. input voltage max8967 toc07 input voltage (v) input current (ua) 4.5 3.5 5 10 15 20 25 30 35 40 45 50 55 60 0 2.5 5.5 step-downs disabled ldos1 = disabled load current (a) 0.1 10 efficiency (%) 1 0.01 0.001 step-down efficiency vs. load current max8967 toc08 50 60 70 80 90 100 40 v out = 1.2v, pfm, remote sense disabled, l = 1h (toko dfe252010r-1r0n) v batt = 4.2v v batt = 3.6v v batt = 3.0v v batt = 2.6v step-down efficiency vs. load current max8967 toc09 load current (a) efficiency (%) 1 0.1 0.01 0.001 10 10 20 30 40 50 60 70 80 90 100 0 v batt = 4.2v v batt = 3.6v v batt = 3.0v v batt = 2.6v v out = 1.2v, fpwm, remote sense disabled, l = 1h (toko dfe252010r-1r0n) max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor maxim integrated
29 typical operating characteristics (continued) (v in_ = v av = 3.6v, v io = 1.8v, typical application circuit , t a = +25 n c, unless otherwise noted.) step-down efficiency vs. load current max8967 toc10 load current (a) efficiency (%) 1 0.1 0.01 0.001 10 55 60 65 70 75 80 85 90 95 100 50 v batt = 4.2v v batt = 3.6v v batt = 3.0v v batt = 2.6v v out = 1.8v, pfm, remote sense disabled, l = 1h (toko dfe252010r-1r0n) step-down efficiency vs. load current max8967 toc11 load current (a) efficiency (%) 1 0.1 0.01 0.001 10 60 65 70 75 80 85 90 95 100 55 v batt = 4.2v v batt = 3.6v v batt = 3.2v v out = 2.8v, pfm, remote sense disabled, l = 1h (toko dfe252010r-1r0n) step-down efficiency vs. load current max8967 toc12 load current (a) efficiency (%) 1 0.1 0.01 0.001 10 55 60 65 70 75 80 85 90 95 100 50 v batt = 4.2v v batt = 3.6v v batt = 3.0v v batt = 2.6v v out = 0.6v, pfm, remote sense disabled, l = 1h (toko dfe252010r-1r0n) step-down load regulation max8967 toc13 load current (ma) output voltage (v) 1.5 1.0 0.5 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 1.180 0 2.0 v batt = 5.5v v batt = 4.2v v batt = 3.6v v batt = 3.0v fpwm, remote sense enabled v id transtion (12.5mv/s slew) max8967 toc14 v out1 40s/div 3.38v 0.6v v in = 4.2v v id transtion (12.5mv/s slew) max8967 toc15 v out1 40s/div 3.38v 0.6v v in = 4.2v max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor maxim integrated
30 typical operating characteristics (continued) (v in_ = v av = 3.6v, v io = 1.8v, typical application circuit , t a = +25 n c, unless otherwise noted.) step-down load transient max8967 toc16 i out v out 20s/div 200ma 5ma 50mv/div ac-coupled v in = 3.6v skip mode v out = 1.2v step-down load transient max8967 toc17 i out 1.2a 200ma 50mv/div ac-coupled v out 20s/div v in = 3.6v v out = 1.2v ldo1 output voltage vs. load curernt max8967 toc18 load current (ma) output voltage (v) 100 50 1.780 1.782 v batt = 4.2v 1.784 1.786 1.788 1.790 1.792 1.794 1.796 1.778 0 150 ldo2 output voltage vs. load curernt max8967 toc19 load current (ma) output voltage (v) 200 100 1.778 1.780 1.782 1.784 1.786 1.788 1.790 1.792 1.794 1.796 1.798 1.776 0 300 v batt = 4.2v ldo3 output voltage vs. load curernt max8967 toc20 load current (ma) output voltage (v) 100 50 1.787 1.788 1.789 1.790 1.791 1.792 1.793 1.794 1.795 1.796 1.786 0 150 v batt = 4.2v ldo4 output voltage vs. load curernt max8967 toc21 load current (ma) output voltage (v) 100 50 1.788 1.789 1.790 1.791 1.792 1.793 1.794 1.795 1.787 0 150 v batt = 4.2v max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor maxim integrated
31 typical operating characteristics (continued) (v in_ = v av = 3.6v, v io = 1.8v, typical application circuit , t a = +25 n c, unless otherwise noted.) ldo5 output voltage vs. load curernt max8967 toc22 load current (ma) output voltage (v) 200 100 1.770 1.775 1.780 1.785 1.790 1.795 1.765 0 300 v batt = 4.2v ldo1 line regulation max8967 toc25 input voltage (v) output voltage (v) 4.5 3.5 1.7785 1.7790 1.7795 1.7800 1.7805 1.7810 1.7780 2.5 5.5 v out = 1.8v, normal mode, i out = 150ma ldo6 output voltage vs. load curernt max8967 toc23 load current (ma) output voltage (v) 100 50 1.786 1.787 1.788 1.789 1.790 1.791 1.792 1.793 1.794 1.785 0 150 v batt = 4.2v ldo2 line regulation max8967 toc26 input voltage (v) output voltage (v) 4.5 3.5 1.7775 1.7780 1.7785 1.7790 1.7795 1.7770 2.5 5.5 v out = 1.8v, normal mode, i out = 300ma max8967 toc24 i out , ldo1 100ma 50mv/div ac-coupled 1ma v out , ldo1 20s/div max8967 toc27 ldo slew control (5mv/s) 3.95v 0.8v v out , ldo1 200s/div v in = 4.2v no load max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor maxim integrated
32 typical operating characteristics (continued) (v in_ = v av = 3.6v, v io = 1.8v, typical application circuit , t a = +25 n c, unless otherwise noted.) max8967 toc28 ldo slew control (100mv/s) 3.95v 0.8v v out , ldo1 10s/div v in = 4.2v no load ldo output voltage accuracy vs. temperature max8967 toc29 temperature (c) output accuracy (%) 50 0 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0.25 -0.25 -50 100 v out,ldo1 = 1v, normal mode step-down switching frequency vs. load current max8967 toc30 load current (ma) switching frequency (mhz) 1500 1000 500 4.25 4.30 4.35 4.40 4.45 4.50 4.55 4.60 4.20 0 2000 v out1 = 1v, fpwm max8967 toc31 light load waveforms 2v/div ac-coupled 50mv/div 0 0 500ma /div i lx1 v lx1 v out1 2s/div i out = 50ma v out = 1.2v v in = 3.6v max8967 toc32 moderate load waveforms 2v/div ac-coupled 50mv/div 0 0 500ma /div i lx1 v lx1 v out1 100s/div i out = 500ma v out = 1.2v v in = 3.6v max8967 toc33 heavy load waveforms ac-coupled 50mv/div i lx1 v lx1 v out1 100ns/div 2v/div 0 0 500ma /div i out = 1a v out = 1.2v v in = 3.6v max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 33 typical applications circuit max8967 in1 pgnd2 inpu t 2.6v to 5.5v in2 av ina 1.7v to 5.5v inb agnd v io 1.65v to 5.5v scl sda en1 en2 v id1 v id2 irqb ldo1 0.8v to 3.95v, 150ma out2 snsp2 lx2 snsn2 1h out2 0.6v to 3.3875v, 2a c ldo1 1 f ldo2 0.8v to 3.95v, 300ma c ldo2 1 f ldo3 0.8v to 3.95v, 150ma c ldo3 1 f ldo4 0.8v to 3.95v, 150ma c ldo4 1 f ldo5 0.8v to 3.95v, 300ma c ldo5 1 f ldo6 0.8v to 3.95v, 150ma c ldo6 1 f out1 snsp1 lx1 pgnd1 snsn1 1h out1 0.6v to 3.3875v, 2a c ou t1 22f c ou t2 22f c in1,2 10f c ina,b 2.2 f pgnd agnd c av 1 f v io v io maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 34 pin description pin configuration pin name function a1 pgnd2 step-down converter 2 power ground. bypass in2 to pgnd2 with a 10 f f ceramic capacitor as close as possible to the ic. a2 lx2 step-down converter 2 inductor switching node. connect a 1 f h inductor from lx2 to out2. lx2 is high impedance when disabled. a3 out2 step-down converter 2 output sense and discharge connection. bypass out2 to pgnd2 with a 22 f f ceramic capacitor. out2 can also be connected to ground through an internal 100 i resistor using an i 2 c command when disabled. a4 agnd analog ground. connect agnd to pgnd_. a5 en2 enable logic input for step-down converter 2. step-down converter 2 can also be enabled through i 2 c. en2 has an internal 800k i pulldown resistor. a6 en1 enable logic input for step-down converter 1. step-down converter 1 can also be enabled through i 2 c. en1 has an internal 800k i pulldown resistor. b1 in2 step-down converter 2 input supply. bypass in2 to pgnd2 with a 10 f f ceramic capacitor as close as possible to the ic. connect in2 to both in1 and av. b2 snsp2 step-down converter 2 positive remote voltage sense. connect snsp2 to the positive terminal of the out2 bypass capacitor. top view (bump side down) a b c d wlp max8967 e lx2 2 snsp2 sda snsp1 lx1 agnd 4 v id2 irqb v id1 av pgnd2 1 in2 scl in1 pgnd1 en2 ldo1 ina ldo2 5 ldo3 en1 ldo4 inb ldo5 6 ldo6 out2 3 snsn2 v io snsn1 out1 + maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 35 pin description (continued) pin name function b3 snsn2 step-down converter 2 negative remote voltage sense. connect snsn2 to the negative terminal of the out2 bypass capacitor. b4 v id2 voltage identification digital 2. to toggle between two step-down converter 2 output voltages, toggle v id2 logic-high and logic-low. v id2 has an internal 800k i pulldown resistor. b5 ldo1 ldo1 output. bypass ldo1 to agnd with a 1 f f ceramic capacitor. b6 ldo4 ldo4 output. bypass ldo4 to agnd with a 1 f f ceramic capacitor. c1 scl i 2 c clock signal. connect scl to v io with a 2.2k i pullup resistor. c2 sda i 2 c data signal. connect sca to v io with a 2.2k i pullup resistor. c3 v io i/o input supply. connect v io to the i 2 c bus masters power supply. c4 irqb interrupt open-drain active-low output. irqb signals if there is a fault. connect irqb to v io with a 100k i pullup resistor. c5 ina input supply for ldos 1, 2, and 3. bypass ina to agnd with a 2.2 f f ceramic capacitor as close as possible to the ic. c6 inb input supply for ldos 4, 5, and 6. bypass inb to agnd with a 2.2 f f ceramic capacitor as close as possible to the ic. d1 in1 power input for step-down converter 1. bypass in1 to pgnd1 as close as possible to the ic. connect in1 to both in2 and av. d2 snsp1 step-down converter 1 positive remote voltage sense. connect snsp1 to the positive terminal of the out1 bypass capacitor. d3 snsn1 step-down converter 1 negative remote voltage sense. connect snsn1 to the negative terminal of the out1 bypass capacitor. d4 v id1 voltage identification digital 1. to toggle between two different step-down converter 1 output voltages toggle v id1 logic-high and logic-low. v id1 has an internal 800k i pulldown resistor. d5 ldo2 ldo2 output. bypass ldo2 to agnd with a 1 f f ceramic capacitor. d6 ldo5 ldo5 output. bypass ldo5 to agnd with a 1 f f ceramic capacitor. e1 pgnd1 step-down converter 1 power ground. bypass in1 to pgnd1 with a 10 f f ceramic capacitor as close as possible to the ic. e2 lx1 inductor connection for buck 1. lx is high impedance when disabled. e3 out1 step-down converter 1 output sense and discharge connection. bypass out1 to pgnd1 with a 22 f f ceramic capacitor. out1 can also be connected to ground through an internal 100 i resistor using an i 2 c command when disabled. e4 av analog input supply. connect av to in1 and in2. bypass av to agnd with 1 f f ceramic capacitor as close as possible to the ic. e5 ldo3 ldo3 output. bypass ldo3 to agnd with a 1 f f ceramic capacitor. e6 ldo6 ldo6 output. bypass ldo6 to agnd with a 1 f f ceramic capacitor. maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 36 general description the max8967s two ultra-low i q step-down converters are ideal for powering modems, applications processor cores, memory, system i/o, and portable devices. in normal operation, these step-down converters consume only 16 f a (typ) of quiescent current. in green mode, the quiescent current is reduced to 5 f a (typ) per converter with reduced load capability. each step-down converter can be independently put into green mode by writing a bit in its control register. step-down converters each step-down converter provides internal feed - back, minimizing external component count. both step-down converter output voltages are programmed through the ics serial interface. a 4.4mhz switching frequency minimizes external component size. dynamic voltage scaling is available to reduce power consumption. both step-down converters feature auto - matic transition from skip mode to fpwm operation. forced pwm operation can be enabled by writing a bit in a control register. interleaved switching the step-down converters high-side switches turn on during opposite clock edges of the oscillator. this helps minimize input current ripple, thus reducing the input capacitance required to reduce input voltage ripple. skip mode/ fpwm operation in the normal operating state, both step-down converters automatically transition from skip mode to fixed-frequency operation as load current increases. for operating modes where lowest output ripple is required, forced pwm switching behavior can be enabled by writing a bit in the appropriate fpwm_ register. see table 3 and table 15 . voltage control using v id both step-down converters feature v id control to reduce power consumption in the loads such as modem and applications processor cores. each v id control allows the converter to transition between two states setup in advance using i 2 c. essentially two voltage states are accessible without the overhead associated with i 2 c con - trol. v id control allows the core voltages to be reduced when the processor clock is throttled back. when exiting sleep mode (by changing the state of v id ), the normal core voltages are restored, providing the optimal operat - ing condition for best system performance. remote output voltage sensing each step-down converters output features remote out - put voltage sensing for improved output voltage accu - racy. the remote sense accommodates a distance that incures up to a 200mv correction in the output voltage. the snsp_ and snsn_ inputs connect directly across the load, with the snsn_ connected to a quiet analog ground near the load, and snsp_ connected directly to the output bypass capacitor. the remote sense feature requires a 1v or greater differ - ence between av and out_ for best performance. the remote sense feature can be disabled through registers to reduce quiescent current consumption. in addition, this feature is disabled during green mode operation. output voltage slew rate both step-down converters feature an adjustable slew rate when increasing or decreasing output voltage. the nominal slew rate is 12.5mv/ f s. two additional slew rates are provided (25mv/ f s and 50mv/ f s), so that faster and slower slew rates can be programmed. an option for fastest possible ramp rate is also provided to allow the converter to operate at current limit for the fastest pos - sible slew rate. when decreasing the output voltage, two settings are provided with a single register bit. when this control bit is set, the converter operates in forced pwm (fpwm) mode with negative inductor current so that the output voltage can be decreased in finite steps at the selected slew rate. when this control bit is reset, the converter operates in skip mode, and the actual slew rate of the output is dependent on the external load, and might not necessar - ily track the slew rate set for falling output voltages. output ripple for normal operation (not in green mode), output ripple should be < 20mv p-p for an output current < 50ma. ripple can be further reduced by increasing output capacitance above the minimum for stable operation. transition from skip to pwm operation should occur at current levels below 50ma. in green mode, the output ripple can increase to 40mv p-p (max) for v out_ = 0.7v. this value can be decreased by adding additional output capacitance. maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 37 green mode operation in green mode, the quiescent current of each of the step-down converters are reduced from 16 f a (typ) to 5 f a (typ). if the output voltages are adjusted during green mode slew rate is very slow. also, output current is limited to 5ma. green mode is enabled by setting bits pwr_[5:4] = 10 in the appropriate converters control register. see table 3 . each converter can be individually selected to enter green mode. discharge resistance the ic provides an internal 100 i discharge resistor for each disabled step-down converter. the discharge resis - tor connection can be enabled and disabled through the naden_ register bit for maximum flexibility. see table 3 . ldo detailed description the ic provides six ldos with adjustable outputs as shown in table 1 . figure 1. power mode state diagram shutdown, standby, and reset table 1. ldo description ldo v in _ range (v) input supply v out range (v) maximum output current (ma) c out ( f f) ldo1 1.7 to 5.5 ina 0.8 to 3.95 150 1 ldo2 1.7 to 5.5 ina 0.8 to 3.95 300 1 ldo3 1.7 to 5.5 ina 0.8 to 3.95 150 1 ldo4 1.7 to 5.5 inb 0.8 to 3.95 150 1 ldo5 1.7 to 5.5 inb 0.8 to 3.95 300 1 ldo6 1.7 to 5.5 inb 0.8 to 3.95 150 1 shutdown v io = en1 = en2 = 0v i q = 0 a standby reference on i q = 20a stepdown converter 1 or 2 is on no valid supply fo r v io /i n1 /i n2 /av or temperature not in rang e no valid supply fo r v io /i n1 /i n2 /a v and en1 = en2 = 0 valid supply fo r v io /i n1/ in 2/ av and temperature in range en_ = 1 pwr1 _[5:4] = 00 an d pwr2 _[5:4] = 00 an d en1 = en2 = 0v an d a valid vio suppl y valid supply fo r v io /i n1/ in 2/ av and en1 = en2 = 0 and temperature in range pwr1 _[5:4] 00 or pwr2 _[5:4] 00 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 38 ldo power modes all ldo regulators have independent enable and disable control through their ldo_pwr[7:6] bits. in addition, each ldo has a special green mode that reduces the quiescent current to 1.5 f a (typ). in green mode, each regulator supports a load of up to 10ma. the load regulation performance degrades proportionally with the reduced load current. several usage options are available for green mode. to force individual regulators to green mode set ldo_ pwr[7:6] = 10. soft-start and dynamic voltage change the ldo regulators have a programmable soft-start rate. when an ldo is enabled, the output voltage ramps to its final voltage at a slew rate of either 5mv/fs or 100mv/fs, depending on the state of the ldo_ss bit. see table 3 and table 20 . the 5mv/ f s ramp rate limits the input inrush current to around 5ma on a 300ma regulator with a 1 f f output capacitor and no load. the 100mv/ f s ramp rate results in a 100ma inrush current with a 1 f f output capacitor and no load, but achieves regulation within 50 f s. the soft- start ramp rate is also the rate of change at the output when switching dynamically between two output voltages without disabling. the soft-start circuitry of the ldos supports starting into a prebiased output. power-ok comparator each regulator includes a power-ok (pok) compara - tor. the pok comparator signals (ldo_pok) indicate when each output has lost regulation (i.e., the output voltage is below v pokthl ). the pok signal has a 25 f s noise immunity filter (v poknf_ ). the pok comparator is disabled in green mode to save power. when any of the pok signals (ldo_pok) go low, then an interrupt is generated. note that the ldos implement a proprietary pok scheme that allows the pok comparator to operate correctly even while the ldo is in its soft-start period. if the ldo is over - loaded when it is in its soft-start period, pok is low. if it is not overloaded during its soft-start period, pok is high. active discharge each linear regulator has an active-discharge resistor feature that can be enabled/disabled with the ldo_ade bit. see table 3 and table 20 . enabling the active discharge feature helps ensure a complete and time - ly power-down of all system peripherals. the default condition of the active-discharge resistor feature is enabled so that whenever vuvlo,ldo_ is below its uvlo threshold, all regulators are disabled with their active discharge resistors turned on. when vuvlo,ldo_ is less than 1.0v, the nmos transistors that control the active discharge resistors lose their gate drive and become open. when the regulator is disabled while the active discharge is disabled, the internal active-discharge resistor is not connected to its output and the output voltage decays at a rate that is determined by the output capacitance and the external load. when the regulator is enabled, the internal active- discharge resistor is not connected to its output. when the regulator is disabled while the active discharge is enabled, an internal active-discharge resistor is con - nected to its output which discharges the energy stored in the output capacitance. adjustable compensation all six ldos have adjustable compensation to facilitate remote capacitor capability. this feature can be used to adjust the compensation of the ldo based on the resis - tance and inductance to the remote capacitor. this abil - ity allows each ldo to be programmed for optimal load transient performance based on the location of its remote capacitor. see table 20 for more details. the ldo com - pensation should be switched only when that ldo is off. if the compensation switches when the ldo is enabled, it causes unknown output glitches, due to switching in uncharged capacitors as compensation changes. overvoltage clamp each ldo has an overvoltage clamp that allows it to sink current when the output voltage is above its target volt - age. this overvoltage clamp is default enabled but can be disabled with ldo_ovclmp_en. see table 3 and table 15 . the following list briefly describes three typi - cal applications scenarios that pertain to the overvoltage clamp. maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 39 ? ldos load leaking current into the ldos output: some ldo loads leak current into an ldo output during certain operating modes. this is typically seen with microprocessor loads. for example, a microprocessor with 3.3v, 2.5v, 1.8v, and 1.0v supply rails is running in standby mode. in this mode, the higher voltage rails can leak currents of several ma into the lower voltage rails. if the 1.0v rail is supplied by an ldo, the ldo output voltage rises based on the amount of leakage current. with the ldo overvoltage clamp enable, when the output voltage rises above its target regulation voltage, the overvoltage clamp sinks current from the output capacitor to bring the output voltage back within regulation. ? negative load transient to 0a: when the ldo load current quickly ramps to 0a (i.e., 300ma to 0a load transient with 1 f s transition time), the output voltage can overshoot (i.e., soar). since the ldo cannot turn off its pass device immedi - ately, the ldo output voltage overshoots. in this instance, when the output voltage sores above target regulation voltage, the overvoltage clamp sinks current from the output capacitor to bring the output voltage back within regulation. ? negative dynamic voltage transition: when the ldo output target voltage is decreased (i.e., 1.2v to 0.8v) when the system loading is light, the energy in the output capacitor tends to hold the output voltage up. when the output voltage is above its target regulation voltage, the overvolt - age clamp sinks current from the output capacitor to bring the output voltage back within regulation. ldo interrupt the power-ok comparators outputs drive a set of inter - rupts. each regulator is capable of generating an inter - rupt, when the output goes out of regulation in normal operation. in green mode, the pok comparators are disabled and the regulators do not generate interrupts. thermal considerations in most applications, the ic does not dissipate much heat due to its high efficiency. but in applications where the ic runs at high ambient temperature with heavy loads, the heat dissipated can exceed the maximum junction tem - perature of the part. if the junction temperature reaches approximately +165 n c, the thermal overload protection is activated. the ic maximum power dissipation depends on the thermal resistance of the ic package and circuit board. the power dissipated in the device is: out1 out2 pd = p (1/ 1 - 1) + p (1/ 2 - 1) where e 1 and e 2 are the efficiencies of each converter while p out1 and p out2 are the output power of each converter. the maximum allowed power dissipation is: max jmax a ja p = (t - t )/ t jmax - t a is the temperature difference between the ics maximum rated junction temperature and the surrounding air, b ja is the thermal resistance of the junction through the pcb, copper traces, and other materials to the surrounding air. digital interface the ic has four types of digital interface: ? two enable pins (en_), one for each step-down converter ? two v id pins (v id_ ), one for each step-down converter ? an interrupt pin, irqb ? a two-wire i 2 c interface the i 2 c interface is use to set the state of the ic while the two enable and two v id pins, one set for each step-down converter, are used to rapidly transition between on/off and two voltage and mode states previously defined using i 2 c communication. enable (en_) two enable logic input pins are provided to allow rapid transitions between on and off for each step-down converter. the enable pins work in conjunction with the i 2 c step-down converter pwr md (mode) bits to control on/off, normal or green mode, and enabling/disabling of remote sense per step-down converter. each converter can be enabled through the dedicated enable pin or through the i 2 c with a logical or function. maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 40 figure 2. i 2 c bit transfer voltage identification digital (v id_ ) two v id_ pins are provided to allow rapid transitions between two previously configured states for each step- down converter. there are multiple registers for output voltage and mode of operation for each converter as well. irqb the irqb is an active-low, open-drain output that signals a fault on any one or more of the step-down converters or ldos. each converter and ldo is individually monitored for its pok status, and thermal shutdown for the entire max8967 is monitored. i 2 c interface an i 2 c-compatible, 2-wire serial interface controls the step-down converter output voltage, ramp rate, operat - ing mode, and synchronization. the serial bus consists of a bidirectional serial-data line (sda) and a serial-clock input (scl). the master initiates data transfer on the bus and generates scl to permit data transfer. i 2 c is an active-low open-drain bus. sda and scl require pullup resistors (500 i or greater). optional resis - tors (24 i ) in series with sda and scl can protect the device inputs from high-voltage spikes on bus lines. series resistors also minimize crosstalk and undershoot on bus signals. bit transfer one data bit is transferred during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. see figure 2 . changes in sda while scl is high are control signals. see the start and stop conditions section for more information. each transmit sequence is framed by a start (s) condi - tion and a stop (p) condition. each data packet is 9 bits long, 8 bits of data followed by the acknowledge bit. the ic supports data transfer rates with scl frequencies up to 400khz. table 2. step-down converter modes en_ i 2 c md bits mode 0 0 0 off 0 0 1 on, green 0 1 0 on, normal, remote sense on 0 1 1 on, normal, remote sense off 1 0 0 on, normal, remote sense on 1 0 1 on, green 1 1 0 on, normal, remote sense on 1 1 1 on, normal, remote sense off data line stable data valid change of data allowed sda scl maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 41 start and stop conditions when the serial interface is inactive, sda and scl idle high. a master device initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda, while scl is high. see figure 3 . a start condition from the master signals the beginning of a transmission to the ic. the master terminates trans - mission by issuing a not-acknowledge (nack) followed by a stop condition. see the acknowledge section for more information. the stop condition frees the bus. to issue a series of commands to the slave, the master can issue repeated start (sr) commands instead of a stop command to maintain control of the bus. in general, a repeated start command is functionally equivalent to a regular start command. when a stop condition or incorrect address is detected, the ic internally disconnects scl from the serial interface until the next start condition, minimizing digital noise and feedthrough. system configuration a device on the i 2 c bus that generates a message is called a transmitter and a device that receives the mes - sage is a receiver. the device that controls the message is the master and the devices that are controlled by the master are called slaves. acknowledge the number of data bytes between the start and stop conditions for the transmitter and receiver are unlimited. each 8-bit byte is followed by an acknowledge bit. the acknowledge bit is a high-level signal put on sda by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver that is addressed must generate an acknowledge after each byte it receives. also, a master receiver must generate an acknowledge after each byte it receives that has been clocked out of the slave transmitter. the device that acknowledges must pull down the data line during the acknowledge clock pulse, so that the data line is stable low during the high period of the acknowledge clock pulse (setup and hold times must also be met). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case, the transmitter must leave sda high to enable the master to generate a stop condition. update of output operation mode if updating the output voltage or operation mode register for the mode that the is currently operating in, the output voltage/operation mode is updated at the same time the ic sends the acknowledge for the i 2 c data byte. figure 3. i 2 c start and stop conditions figure 4. i 2 c acknowledge sda scl start condition stop condition sda by master sda by slave scl 1 2 8 9 acknowledge clock pulse for acknowledgement d7 d6 d0 start condition not acknowledge maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 42 figure 5. i 2 c write operation slave address a bus master initiates communication ic by issuing a start condition followed by the slave address. the slave address byte consists of 7 address bits (1100011x) and a read/write bit (r/ w ). after receiving the proper address, the ic issues an acknowledge by pulling sda low during the ninth clock cycle. the ic uses a default i 2 c slave address of c6h. there are two other slave addresses (c8h and cah) that can be assigned. contact the factory for details. see the selector guide . write operations the ic recognizes the write byte protocol as defined in the smbus specification. the write byte protocol allows the i 2 c master device to send 1 byte of data to the slave device. the write byte protocol requires a register pointer address for the subsequent write. the ic acknowledges any register pointer even though only a subset of those registers actually exists in the device. the write byte pro - tocol is as follows: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a write bit. 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends an 8-bit register pointer. 5) the slave acknowledges the register pointer. 6) the master sends a data byte. 7) the slave acknowledges the data byte. 8) the slave updates with the new data. 9) the master sends a stop condition. 1 s number of bits r/w slave address 7 0 18 register pointer 11 8 data 1 p 1 slave to master master to slave legend a) writing to a single register with the write byte protocol 1 s number of bits r/w slave address 7 0 18 register pointer x 1 a 18 data x 1 b) writing to multiple registers 8 data x + n - 1 18 data x + n 1 number of bit s p 8 data x + 1 1 a a a a a a a a maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 43 in addition to the write-byte protocol, the ic can write to multiple registers as shown in figure 5 . this protocol allows the i 2 c master device to address the slave only once and then send data to a sequential block of regis - ters starting at the specified register pointer. use the following procedure to write to a sequential block of registers: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a write bit. 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends the 8-bit register pointer of the first register to write. 5) the slave acknowledges the register pointer. 6) the master sends a data byte. 7) the slave acknowledges the data byte. 8) the slave updates with the new data. 9) steps 6 to 8 are repeated for as many registers in the block, with the register pointer automatically incremented each time. 10) the master sends a stop condition. read operations the method for reading a single register (byte) is shown below. to read a single register: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a write bit. 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends an 8-bit register pointer. 5) the slave acknowledges the register pointer. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address followed by a read bit. 8) the slave assets an acknowledge by pulling sda low. 9) the slave sends the 8-bit data (contents of the register). 10) the master assets a not acknowledge by keeping sda high. 11) the master sends a stop condition. figure 6. i 2 c read operation 1 s number of bits r/w slave address 7 0 18 register pointer 11 17 slave address 1 1 slave to master master to slave legend a) reading a single register 1 s number of bits r/w slave address 7 0 18 register pointer x 1 a 11 7 slave address 1 b) reading multiple registers ... 8 data x+1 1 8 data x+n-1 1 number of bits ... 8 data x 1 r/w a a aa a a sr a 1 8 data 1 p 1 a a 1 1 sr ... 8 data x+n 11 a p r/w maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 44 in addition, the ic can read a block of multiple sequential registers as shown in section b of figure 6 . use the fol - lowing procedure to read a sequential block of registers: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a write bit. 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends an 8-bit register pointer of the first register in the block. 5) the slave acknowledges the register pointer. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address followed by a read bit. 8) the slave assets an acknowledge by pulling sda low. 9) the slave sends the 8-bit data (contents of the register). 10) the master assets an acknowledge by pulling sda low when there is more data to read, or a not acknowledge by keeping sda high when all data has been read. 11) steps 9 and 10 are repeated for as many registers in the block, with the register pointer automatically incremented each time. 12) the master sends a stop condition. figure 7. i 2 c timing diagram scl sda t r t f t buf start condition stop condition repeated start condition start condition t su,sto t hd,sta t su,sta t hd,dat t su,dat t low t high t hd,sta maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 45 i 2 c commands register reset all resisters associated with the ics i 2 c interface are reset to their default values when the voltage applied to v io drops below the 0.4v threshold. see the electrical characteristics table. the slave address of the ic is 0xc6. i 2 c high level register map table 3. i 2 c high level register map register description bit 7 msb 6 5 4 3 2 1 0 lsb 0x00 id id[7:0] 0x01 chip configuration freq[2:0] rsvd rsvd rsvd rsvd rsvd 0x02 step-down 1 voltage v id high vout_b1_vidh[7:0] 0x03 step-down 1 voltage v id low vout_b1_vidl[7:0] 0x04 step-down 1 configuration v id high slew1h[7:6] pwr1h[5:4] naden1h fpwm1h rsvd fall slew1h 0x05 step-down 1 configuration v id low slew1l[7:6] pwr1l[5:4] naden1l fpwm1l rsvd fall slew1l 0x06 step-down 2 voltage v id high vout_b2_vidh[7:0] 0x07 step-down 2 voltage v id low vout_b2_vidl[7:0] 0x08 step-down 2 configuration v id high slew2h[7:6] pwr2h[5:4] naden2h fpwm2h rsvd fall slew2h 0x09 step-down 2 configuration v id low slew2l[7:6] pwr2l[5:4] naden2l fpwm2l rsvd fall slew2l 0x0b status pnok1 pnok2 th ldo_ pnok rsvd rsvd rsvd rsvd 0x0c interrupt pnok1_ int pnok2_ int th_int ldo_ pnok_ int rsvd rsvd rsvd rsvd 0x0d interrupt mask pnok1m pnok2m thm ldo_ pnokm rsvd rsvd rsvd rsvd 0x0e ldo 1 configuration 1 ldo1pwr[7:6] ldo1tv[5:0] 0x0f ldo 1 configuration 2 ldo1ov clmp_en rsvd ldo1comp[5:4] ldo1pok rsvd ldo1 ade ldo1ss 0x10 ldo 2 configuration 1 ldo2pwr[7:6] ldo2tv[5:0] 0x11 ldo 2 configuration 2 ldo2ov clmp_en rsvd ldo2comp[5:4] ldo2pok rsvd ldo2 ade ldo2ss 0x12 ldo 3 configuration 1 ldo3pwr[7:6] ldo3tv[5:0] 0x13 ldo 3 configuration 2 ldo3ov clmp_en rsvd ldo3comp[5:4] ldo3pok rsvd ldo3 ade ldo3ss maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 46 table 3. i 2 c high level register map (continued) table 4. id register table 5. chip configuration register command name id i 2 c address max8967 i 2 c address command code 0x00 access type read only reset condition hard wired, not reset bit name description default 7C0 id[7:0] code is a unique chip version identifier 0x66 command name chip configuration i 2 c address max8967 i 2 c address command code 0x01 access type read/write reset condition power-up/chip reset bit name description default 7, 6, 5 freq[2:0] switching frequency selection bits 0b000 000 = 4.4mhz 100 = 4.2mhz 001 = 4.8mhz 101 = rsvd 010 = 4.0mhz 110 = 4.6mhz 011 = rsvd 111 = rsvd 4C0 reserved 0b0 register description bit 7 msb 6 5 4 3 2 1 0 lsb 0x14 ldo 4 configuration 1 ldo4pwr[7:6] ldo4tv[5:0] 0x15 ldo 4 configuration 2 ldo4ov clmp_en rsvd ldo4comp[5:4] ldo4pok rsvd ldo4 ade ldo4ss 0x16 ldo 5 configuration 1 ldo5pwr[7:6] ldo5tv[5:0] 0x17 ldo 5 configuration 2 ldo5ov clmp_en rsvd ldo5comp[5:4] ldo5pok rsvd ldo5 ade ldo5ss 0x18 ldo 6 configuration 1 ldo6pwr[7:6] ldo6tv[5:0] 0x19 ldo 6 configuration 2 ldo6ov clmp_en rsvd ldo6comp[5:4] ldo6pok rsvd ldo6 ade ldo6ss 0x1b ldo int rsvd l06_int l05_int l04_int l03_int l02_int l01_int 0x1c ldo intm rsvd l06_intm l05_intm l04_intm l03_intm l02_intm l01_intm maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 47 table 6. step-down 1 output voltage vid high table 7. step-down 1 output voltage vid low table 8. step-down 1 configuration register vid high table 9. step-down 1 configuration register vid low command name step-down converter 1 voltage vid high i 2 c address max8967 i 2 c address command code 0x02 access type read/write reset condition power-up/chip reset command name step-down converter 1 voltage vid low i 2 c address max8967 i 2 c address command code 0x03 access type read/write reset condition power-up/chip reset command name step-down converter 1 configuration vid high i 2 c address max8967 i 2 c address command code 0x04 access type read/write reset condition power-up/chip reset command name step-down converter 1 configuration vid low i 2 c address max8967 i 2 c address command code 0x05 access type read/write reset condition power-up/chip reset bit name description default 7:0 vout_ b1_vidh [7:0] see table 14 0x00 bit name description default 7C0 vout_b1_vidl [7:0] see table 14 0x30 bit name description default 7C0 see table 15 see table 15 0x00 bit name description default 7C0 see table 15 see table 15 0x00 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 48 table 10. step-down 2 voltage register vid high table 11. step-down 2 output voltage vid low table 12. step-down 2 configuration register vid high table 13. step-down 2 configuration register vid low command name step-down 2 voltage vid high i 2 c address max8967 i 2 c address command code 0x06 access type read/write reset condition power-up/chip reset command name step-down 2 voltage vid low i 2 c address max8967 i 2 c address command code 0x07 access type read/write reset condition power-up/chip reset command name step-down 2 configuration vid high i 2 c address max8967 i 2 c address command code 0x08 access type read/write reset condition power-up/chip reset bit name description default 7C0 vout_b2_vidh[7:0] see table 14 0x00 bit name description default 7C0 vout_b2_vidl[7:0] see table 14 0x30 bit name description default 7C0 see table 15 see table 15 0x00 command name step-down 2 configuration vid low i 2 c address max8967 i 2 c address command code 0x09 access type read/write reset condition power-up/chip reset bit name description default 7C0 see table 15 see table 15 0x00 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 49 table 14. step-down output voltage table bit description default vout_b_ vid_[7:0] 0x00 = 0.6000v 0x20 = 1.0000v 0x40 = 1.4000v 0x60 = 1.8000v 0x80 = 2.2000v 0xa0 = 2.6000v 0xc0 = 3.0000v see the electrical characteristics table. 0x01 = 0.6125v 0x21 = 1.0125v 0x41 = 1.4125v 0x61 = 1.8125v 0x81 = 2.2125v 0xa1 = 2.6125v 0xc1 = 3.0125v 0x02 = 0.6250v 0x22 = 1.0250v 0x42 = 1.4250v 0x62 = 1.8250v 0x82 = 2.2250v 0xa2 = 2.6250v 0xc2 = 3.0250v 0x03 = 0.6375v 0x23 = 1.0375v 0x43 = 1.4375v 0x63 = 1.8375v 0x83 = 2.2375v 0xa3 = 2.6375v 0xc3 = 3.0375v 0x04 = 0.6500v 0x24 = 1.0500v 0x44 = 1.4500v 0x64 = 1.8500v 0x84 = 2.2500v 0xa4 = 2.6500v 0xc4 = 3.0500v 0x05 = 0.6625v 0x25 = 1.0625v 0x45 = 1.4625v 0x65 = 1.8625v 0x85 = 2.2625v 0xa5 = 2.6625v 0xc5 = 3.0625v 0x06 = 0.6750v 0x26 = 1.0750v 0x46 = 1.4750v 0x66 = 1.8750v 0x86 = 2.2750v 0xa6 = 2.6750v 0xc6 = 3.0750v 0x07 = 0.6875v 0x27 = 1.0875v 0x47 = 1.4875v 0x67 = 1.8875v 0x87 = 2.2875v 0xa7 = 2.6875v 0xc7 = 3.0875v 0x08 = 0.7000v 0x28 = 1.1000v 0x48 = 1.5000v 0x68 = 1.9000v 0x88 = 2.3000v 0xa8 = 2.7000v 0xc8 = 3.1000v 0x09 = 0.7125v 0x29 = 1.1125v 0x49 = 1.5125v 0x69 = 1.9125v 0x89 = 2.3125v 0xa9 = 2.7125v 0xc9 = 3.1125v 0x0a = 0.7250v 0x2a = 1.1250v 0x4a = 1.5250v 0x6a = 1.9250v 0x8a = 2.3250v 0xaa = 2.7250v 0xca = 3.1250v 0x0b = 0.7375v 0x2b = 1.1375v 0x4b = 1.5375v 0x6b = 1.9375v 0x8b = 2.3375v 0xab = 2.7375v 0xcb = 3.1375v 0x0c = 0.7500v 0x2c = 1.1500v 0x4c = 1.5500v 0x6c = 1.9500v 0x8c = 2.3500v 0xac = 2.7500v 0xcc = 3.1500v 0x0d = 0.7625v 0x2d = 1.1625v 0x4d = 1.5625v 0x6d = 1.9625v 0x8d = 2.3625v 0xad = 2.7625v 0xcd = 3.1625v 0x0e = 0.7750v 0x2e = 1.1750v 0x4e = 1.5750v 0x6e = 1.9750v 0x8e = 2.3750v 0xae = 2.7750v 0xce = 3.1750v 0x0f = 0.7875v 0x2f = 1.1875v 0x4f = 1.5875v 0x6f = 1.9875v 0x8f = 2.3875v 0xaf = 2.7875v 0xcf = 3.1875v 0x10 = 0.8000v 0x30 = 1.2000v 0x50 = 1.6000v 0x70 = 2.0000v 0x90 = 2.4000v 0xb0 = 2.8000v 0xd0 = 3.2000v 0x11 = 0.8125v 0x31 = 1.2125v 0x51 = 1.6125v 0x71 = 2.0125v 0x91 = 2.4125v 0xb1 = 2.8125v 0xd1 = 3.2125v 0x12 = 0.8250v 0x32 = 1.2250v 0x52 = 1.6250v 0x72 = 2.0250v 0x92 = 2.4250v 0xb2 = 2.8250v 0xd2 = 3.2250v 0x13 = 0.8375v 0x33 = 1.2375v 0x53 = 1.6375v 0x73 = 2.0375v 0x93 = 2.4375v 0xb3 = 2.8375v 0xd3 = 3.2375v maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 50 table 14. step-down output voltage table (continued) bit description default vout_ b_ vid_[7:0] 0x14 = 0.8500v 0x34 = 1.2500v 0x54 = 1.6500v 0x74 = 2.0500v 0x94 = 2.4500v 0xb4 = 2.8500v 0xd4 = 3.2500v see the electrical characteristics table. 0x15 = 0.8625v 0x35 = 1.2625v 0x55 = 1.6625v 0x75 = 2.0625v 0x95 = 2.4625v 0xb5 = 2.8625v 0xd5 = 3.2625v 0x16 = 0.8750v 0x36 = 1.2750v 0x56 = 1.6750v 0x76 = 2.0750v 0x96 = 2.4750v 0xb6 = 2.8750v 0xd6 = 3.2750v 0x17 = 0.8875v 0x37 = 1.2875v 0x57 = 1.6875v 0x77= 2.0875v 0x97 = 2.4875v 0xb7 = 2.8875v 0xd7 = 3.2875v 0x18 = 0.9000v 0x38 = 1.3000v 0x58 = 1.7000v 0x78 = 2.1000v 0x98 = 2.5000v 0xb8 = 2.9000v 0xd8 = 3.3000v 0x19 = 0.9125v 0x39 = 1.3125v 0x59 = 1.7125v 0x79 = 2.1125v 0x99 = 2.5125v 0xb9 = 2.9125v 0xd9 = 3.3125v 0x1a = 0.9250v 0x3a = 1.3250v 0x5a = 1.7250v 0x7a = 2.1250v 0x9a = 2.5250v 0xba = 2.9250v 0xda = 3.3250v 0x1b = 0.9375v 0x3b = 1.3375v 0x5b = 1.7375v 0x7b = 2.1375v 0x9b = 2.5375v 0xbb = 2.9375v 0xdb = 3.3375v 0x1c = 0.9500v 0x3c = 1.3500v 0x5c = 1.7500v 0x7c = 2.1500v 0x9c = 2.5500v 0xbc = 2.9500v 0xdc = 3.3500v 0x1d = 0.9625v 0x3d = 1.3625v 0x5d = 1.7625v 0x7d = 2.1625v 0x9d = 2.5625v 0xbd = 2.9625v 0xdd = 3.3625v 0x1e = 0.9750v 0x3e = 1.3750v 0x5e = 1.7750v 0x7e = 2.1750v 0x9e = 2.5750v 0xbe = 2.9750v 0xde = 3.3750v 0x1f = 0.9875v 0x3f = 1.3875v 0x5f = 1.7875v 0x7f = 2.1875v 0x9f = 2.5875v 0xbf = 2.9875v 0xdf = 3.3875v maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 51 table 15. step-down configuration table bit name description default 0 fallslew_ active-low step-down converter falling slew rate enable 0 = the slew rate control circuit is active when the output voltage is decreased. the desired regulation voltage is decreased in 12.5mv steps, and forced pwm mode is enabled so that negative inductor current can be used to pull energy out of the output capacitor. 1 = the slew rate control circuit is disabled when the output voltage is decreased. the desired regulation voltage is decreased in 12.5mv steps, but it is up to the external load to drain energy from the output capacitor in order to pull down on the output voltage. 0b0 1 rsvd reserved 0b0 2 fpwm_ step-down forced pwm mode enable 0 = step-down converter automatically skips pulses under light load conditions, and transfers to fixed frequency operation as the load current increases. 1 = step-down converter operates with fixed frequency under all load conditions. 0b0 3 naden_ active-low buck converter active discharge enable 0 = the active discharge function is enabled. when the buck converter is disabled, an internal 100 i discharge resistor is connected to the output to discharge the energy stored in the output capacitor. when the buck converter is enabled, the discharge resistor is disconnected from the output. 1 = the active discharge function is disabled. when the buck converter is disabled, the internal 100 i discharge resistor is not connected to the output, and the discharge rate is dependent on the output capacitance and the load present. when the buck converter is enabled, the discharge resistor is disconnected from the output. 0b0 5:4 pwr_[5:4] step-down power mode configuration. these bits determine the mode of operation for this converter. 00 = disabled 01 = normal operation mode with remote sense disabled 10 = green mode 11 = normal operation mode with remote sense enabled 0b00 7:6 slew_[7:6] step-down rising slew rate 00 = 12.5mv/ f s ramp rate 01 = 25mv/ f s ramp rate 10 = 50mv/ f s ramp rate 11 = no slew rate control. output voltage increases as fast as the current limit allows. 0b00 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 52 table 16. status table 17. interrupt command name status i 2 c address max8967 i 2 c address command code 0x0b access type read only. status is masked by the interrupt mask register and is cleared by reading related interrupt register bits. reset condition power-up/chip reset/0b1 written to bit command name interrupt i 2 c address max8967 i 2 c address command code 0x0c access type readclear on read reset condition power-up/chip reset/0b1 written to bit bit name description default 7 pnok1 0 = step-down converter 1 is on. 1 = step-down converter 1 is off or faulted. 0b1 6 pnok2 0 = step-down converter 2 is on. 1 = step-down converter 2 is off or faulted. 0b1 5 th 0 = temperature is below the thermal shutdown threshold. 1 = temperature exceeds the thermal shutdown threshold. 0b0 4 ldo_pnok 0 = one or more ldos are off or above the pok threshold. 0 = one or more ldos are on and below the pok threshold. 0b0 3 rsvd reserved 0b1 2 rsvd reserved 0b1 1 rsvd reserved 0b1 0 rsvd reserved 0b1 bit name description default 7 pnok1_int step-down 1 interrupt bit 0 = output is normal 1 = output has fallen below the power-ok threshold. 0b0 6 pnok2_int step-down 2 interrupt bit 0 = output is normal 1 = output has fallen below the power-ok threshold. 0b0 5 th_int thermal interrupt bit 0 = die temperature is normal 1 = die temperature has exceeded thermal shutdown threshold 0b0 4 ldo_pnok_int one or more ldo power-ok levels have not been maintained. 0b0 3 rsvd reserved 0b0 2 rsvd reserved 0b0 1 rsvd reserved 0b0 0 rsvd reserved 0b0 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 53 table 18. interrupt mask command name interrupt mask i 2 c address max8967 i 2 c address command code 0x0d access type readCclear on read reset condition power-up/chip reset/0b1 written to bit bit name description default 7 pnok1m step-down 1 interrupt mask bit 0 = interrupt is unmasked. 1 = interrupt is masked. 0b1 6 pnok2m step-down 2 interrupt mask bit 0 = interrupt is unmasked. 1 = interrupt is masked. 0b1 5 thm thermal interrupt mask bit 0 = interrupt is unmasked. 1 = interrupt is masked. 0b1 4 ldo_pnokm ldo interrupt mask bit 0 = interrupt is unmasked. 1 = interrupt is masked. 0b1 3 rsvd reserved 0b1 2 rsvd reserved 0b0 1 rsvd reserved 0b0 0 rsvd reserved 0b0 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 54 table 19. ldo_ configuration 1 register register name ldo_ configuration 1 register address see table 3 access type read/write reset condition power-up/chip reset bit name description default 7, 6 ldo_pwr [7:6] ldo power mode configuration 00 = output disabled 01 = output disabled 10 = green mode 11 = normal mode 0b00 5C0 ldo_tv[5:0] sets the target voltage of the ldo. programmed in 0.05v steps. 0b00 0x00 = 0.80v 0x0a = 1.30v 0x14 = 1.80v 0x1e = 2.30v 0x28 = 2.80v 0x32 = 3.30v 0x3c = 3.80v 0x01 = 0.85v 0x0b = 1.35v 0x15 = 1.85v 0x1f = 2.35v 0x29 = 2.85v 0x33 = 3.35v 0x3d = 3.85v 0x02 = 0.90v 0x0c = 1.40v 0x16 = 1.90v 0x20 = 2.40v 0x2a = 2.90v 0x34 = 3.40v 0x3e = 3.90v 0x03 = 0.95v 0x0d = 1.45v 0x17 = 1.95v 0x21 = 2.45v 0x2b = 2.95v 0x35 = 3.45v 0x3f = 3.95v 0x04 = 1.00v 0x0e = 1.50v 0x18 = 2.00v 0x22 = 2.50v 0x2c = 3.00v 0x36 = 3.50v 0x05 = 1.05v 0x0f = 1.55v 0x19 = 2.05v 0x23 = 2.55v 0x2d = 3.05v 0x37 = 3.55v 0x06 = 1.10v 0x10 = 1.60v 0x1a = 2.10v 0x24 = 2.60v 0x2e = 3.10v 0x38 = 3.60v 0x07 = 1.15v 0x11 = 1.65v 0x1b = 2.15v 0x25 = 2.65v 0x2f = 3.15v 0x39 = 3.65v 0x08 = 1.20v 0x12 = 1.70v 0x1c = 2.20v 0x26 = 2.70v 0x30 = 3.20v 0x3a = 3.70v 0x09 = 1.25v 0x13 = 1.75v 0x1d = 2.25v 0x27 = 2.75v 0x31 = 3.25v 0x3b = 3.75v maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 55 table 20. ldo_ configuration 2 register register name ldo_ configuration 2 register address see table 3. access type read only for bit 3, and read/write for the rest reset condition power-up/chip reset bit name description default 7 ldo_ovclmp_en overvoltage clamp enable 0 = overvoltage clamp disabled. 1 = overvoltage clamp enabled. 0b1 6 rsvd reserved 0b0 5, 4 ldo_comp ldo compensation 00 = assume 50m i /5nh trace impedance to remote capacitor. 01 = assume 100m i /10nh trace impedance to remote capacitor. 10 = assume 50m i to 200m i /5nh to 20nh trace impedance to remote capacitor. 11 = assume 100m i to 400m i /10nh to 40nh trace impedance to remote capacitor. note: the ldo_comp bits should only be changed with the ldo is disabled. if the compensation bits are changed when the ldo is enabled, the output voltage glitches as the compensation changes. 0b01 3 ldo_pok voltage ok status bit 0 = the voltage is less than the pok threshold and the device is in normal mode. 1 = the voltage is above the pok threshold or the ldo is operating in its green mode or the ldo is disabled. 0b0 2 rsvd reserved 1 ldo_ade active discharge enable 0 = the active discharge function is disabled. 1 = the active discharge function is enabled. 0b1 0 ldo_ss sets the ldo soft-start slew rate (applies to both startup and output voltage setting changes) 0 = fast startup and dynamic voltage change100mv/ f s. 1 = slow startup and dynamic voltage change5mv/ f s. 0b1 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 56 table 21. ldo_int register register name ldo_int register address 0x1b access type readclear on read reset condition power-up/chip reset bit name description default 7, 6 rsvd reserved 5 l06_int ldo6 interrupt bit 0 = ldo output is normal. 1 = ldo output has fallen below the power-ok threshold. 0b0 4 l05_int ldo5 interrupt bit 0 = ldo output is normal. 1 = ldo output has fallen below the power-ok threshold. 0b0 3 l04_int ldo4 interrupt bit 0 = ldo output is normal. 1 = ldo output has fallen below the power-ok threshold. 0b0 2 l03_int ldo3 interrupt bit 0 = ldo output is normal. 1 = ldo output has fallen below the power-ok threshold. 0b0 1 l02_int ldo2 interrupt bit 0 = ldo output is normal. 1 = ldo output has fallen below the power-ok threshold. 0b0 0 l01_int ldo1 interrupt bit 0 = ldo output is normal. 1 = ldo output has fallen below the power-ok threshold. 0b0 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 57 table 22. ldo_intm register applications information inductor selection each step-down converter operates with a 1 f h nominal inductance. it is recommended to use an inductor with a dcr less than 50m i to reduce i 2 r losses. output capacitor selection the ic is designed to operate with at least a 22f ceramic capacitor (x5r rated) connected to each step- down converter output. note that a significant share of each outputs capacitance can be placed as bypassing at the load. a 1f (x5r rated ceramic capacitor is required for each ldo output. the capacitor can be remotely placed away from the ic and the appropriate compensation can be selected through an i 2 c command. see table 20 . input capacitor selection since ripple cancelation is used, the worst case condition is if one supply is operating at near its 2a maximum while the other supply is providing very little current. since the ic can normally be connected to a node with significant capacitance, only 4.7 f f need be applied locally. a 10 f f ceramic capacitor with x5r rating is recommended. pc b layout nearly all noise generated by the ic is found across in1, in2, and pgnd_ pins. the bypass capacitors for these pins should be placed closest to the ic. pgnd_ and agnd should be connected only after the pgnd_ pins connect to its corresponding step-down converters input capaci - tor. both step-down converters have remote sensing which accommodates a distance that incurs up to a 200mv cor - rection in the output voltage. refer to the max8967 ev kit for more details. register name ldo_intm register address 0x1c access type readclear on read reset condition power-up/chip reset bit name description default 7, 6 rsvd reserved 0b11 5 l06_intm ldo6 interrupt mask bit 0 = interrupt is unmasked. 1 = interrupt is masked. 0b1 4 l05_intm ldo5 interrupt mask bit 0 = interrupt is unmasked. 1 = interrupt is masked. 0b1 3 l04_intm ldo4 interrupt mask bit 0 = interrupt is unmasked. 1 = interrupt is masked. 0b1 2 l03_intm ldo3 interrupt mask bit 0 = interrupt is unmasked. 1 = interrupt is masked. 0b1 1 l02_intm ldo2 interrupt mask bit 0 = interrupt is unmasked. 1 = interrupt is masked. 0b1 0 l01_intm ldo1 interrupt mask bit 0 = interrupt is unmasked. 1 = interrupt is masked. 0b1 maxim integrated
max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor 58 ordering information + denotes a lead (pb)-free/rohs-compliant package. package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos part pin-package temp range buck out1 (v) buck out2 (v) max8967ewv+t 30 wlp -40 n c to +85 n c 1.20 1.20 max8967aewv+t 30 wlp -40 n c to +85 n c 1.20 1.80 max8967bewv+t 30 wlp -40 n c to +85 n c 1.20 2.80 max8967cewv+t 30 wlp -40 n c to +85 n c 1.20 3.20 package type package code outline no. land pattern no. 30 wlp w302b2+2 21-0548 refer to application note 1891 maxim integrated
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 59 ? 2012 maxim integrated maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 12/12 initial release max8967 dual 2a step-down converters with 6 ldos for baseband and applications processor

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